Universal Memory Controller Functional Verification Training
Universal Memory controller design support various types of memories like SRAM, SDRAM, Flash, ROM and Synchronous memory devices. It supports 8 chip selects with configurable memory sizes and timing behavior. This project provides student with detailed exposure to complete project flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.
- Universal memory controller and memory detailed overview
- Design specification
- Listing down features, scenarios
- Developing testplan
- Testbench architecture
- Testbench component coding
- Functional coverage coding
- Register model coding and integration
- Assertion development
- Testbench component integration
- Sanity Testcase coding
- Functional Testcase coding
- Regression setup using Python
- Regression debug
- coverage report generation and analysis
|Course||Universal Memory Controller|
|Mode of Training||Classroom training at Institute(ORR, Banaswadi), |
Online training using live training sessions
|Fee||INR 7000 +GST at 18%(Classroom) |
INR 8000 + GST at 18%(online)
|Certificate||Issued based on 50% assignment completion as criteria|
|Trainer||12+ Years exp in RTL design & Functional verification|
What are the Course Prerequisites?
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
What if I miss few sessions during course?
- Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- Universal memory controller specification
- Verification plan
- Complete testbench code
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects