Course Overview

DDR1 to DDR4, LPDDR1 to LPDDR3 Training

• DDR memory architecture, pages, banks, rows, columns
• DDR bandwidth, transfer rate
• DDR Interface signals
• DDR commands, timing diagrams
• DDR Mode registers
• DDR clock frequency, limitation
• DDR initialisation and power up sequence
• DDR Training: Write levelling, Read training, CA Training, ZQ Calibration
• DDR use in SoC
• LP, PC DDR’s

DDR PHY basics

• • Architecture
  • Sub components

DDR Controller concepts

DDR Training(VG-DDR) Schedule

• Next Batch:Adhoc(based on minimum number of students enroling for the course)
  • Currently there is no live sessions planned. You may enrol for e-learning course for self paced learning, with option to join upcoming batch with no additional cost. Trainer will be accessible for doubt clarifications.
• Duration: 6 weeks
• Fee : INR 7,000 +GST at 18%
• Certificate of course completion

Registration:

• Attend Demo Session before registering for course

Course Material Shared

• DDR3, DDR4 protocol JEDEC specifications
• sample testbench code for DDR protocol
• Short notes/checklist

Experienced Trainer

• 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
• Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
• Experience of working on multiple complex module level projects