Term DDR in resume opens up quite a few job opportunities!!..that is the importance of DDR in current SoC’s..
DDR is an essential component of every complex SOC. It requires every engineer working on SoC to be well versed with DDR protocol concepts including DDR controller, DDR PHY, DDR memory, etc. The course focus on teaching DDR3, DDR4, timing diagrams, training sequence, DDR controller design concepts and DDRPHY concepts.
DDR2, DDR3, DDR4 Training
- DDR memory architecture, pages, banks, rows, columns
- DDR bandwidth, transfer rate
- DDR Interface signals
- DDR commands, timing diagrams
- DDR Mode registers
- DDR clock frequency, limitation
- DDR initialization and power up sequence
- DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
- DDR use in SoC
- LP, PC DDR’s
DDR PHY basics
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- Architecture
- Sub components
DDR Controller concepts
DDR Training(VG-DDR) Schedule
- Next Batch: ad hoc basis
- Duration: 5 weeks
- Fee : INR 6,000
- DDR controller design & verification course is offered as part of DDR practical training(not part of this course)
- Certificate of course completion
Registration:
- Attend Demo Session before registering for course
What are the Course Prerequisites?
- Exposure to basic memory concepts like SRAM, FLash, etc
- Exposure to digital design concepts
Does course cover practical sessions on protocols?
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- Dedicated sessions planned to train student on Protocol specific TB component coding
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Course Material Shared
- DDR3, DDR4 protocol JEDEC specifications
- sample testbench code for DDR protocol
- Short notes/checklist
Target Audience:
- Verification engineers with no prior exposure to DDR protocol.
- Verification engineers looking for better career opportunities, and looking to improve their profile
- Engineering college faculty looking to enhance their VLSI skill set
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
