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AXI2OCP bridge verification using SV & UVM
Universal Memory Controller verification using SV & UVM
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Home
Courses
Freshers
Functional / ASIC verification
Physical Design
FPGA system design
Design for testability (DFT)
Custom/Analog layout
Embedded systems
Working professionals
RTL design and integration
Functional verification
Physical Design
Design for testability (DFT)
Custom and Analog Layout
Synthesis and STA
IR Drop analysis using RedHawk
Protocol Courses
PCIe Gen5
AMBA(AXI, AHB, and APB)
DDR to DDR4, LPDDR to LPDDR4
DDR5
SPI, I2C and UART
AMBA CHI Training
USB2.0 & USB3.x
USB4
ACE protocol
Display Port
NVMe
CXL Training
Short Term Courses
Verilog
System Verilog
UVM course
UVM advanced course with multiple projects
Advanced digital design
VHDL
Systemverilog assertions and coverage
UVM Register model training
LEC formal
Lint and CDC
Formal property verification
SoC
SOC Design & Verification
Functional verification debug techniques
ARM v8 architecture
Power Aware Verification
RISC-V ISA
Gate level Simulations(GLS)
Scripting
PERL Training
Python Training
TCL scripting training
Linux training
Gvim training
Shell Scripting training
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FUNCTIONAL VERIFICATION interview preparation
Physical Design interview preparation
DFT interview preparation
Embedded system interview preparation
FPGA interview preparation
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VERILOG
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System Verilog for Design & Verification
UVM FUNCTIONAL VERIFICATION
UVM ADVANCED COURSE AND MULTIPLE PROJECTS
System Verilog Constraints, coverage and assertions
COURSE
UVM Register model development
LEC formal verification(LEC)
LINT & CDC - Deep dive
Formal property verification
ADVANCED DIGITAL DESIGN COURSE
VHDL
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USB2.0 Functional Verification
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