VLSI Flow can be majorly be divided in to 11 steps as below. These can be majorly divided in to two categories, VLSI Front end flow and VLSI Back end flow. VLSI Front end flow consists of design flow starting from architecture to functional verification. Rest of the flow starting from Synthesis to Physical verification is VLSI Back end flow. Assuming team has 50 engineers.
Below shows possible distribution of team members in various domains(value in brackets is number of engineers)
– RTL Design (2, SOC development mostly works on IP reuse, most of IP development happens out side India)
– RTL Integration (2)
– Functional verification (13)
– Formal verification (1)
– Power aware verification (1)
– Synthesis (2)
– Physical Design (13)
– STA (3)
– DFT (2)
– Custom Layout (4)
– Physical Verification (4)
– Post Silicon validation (3)
VLSI Design flow starts with requirments, then it gets developed as a architecture, which is implemented using Verilog RTL(or VHDL) coding. This RTL code is verified using Systemverilog & UVM (C + SV for SOC) based testbenches. This stage is called functional verification. The flow till this stage is called as VLSI Front end flow(similar to software job). This is more programming oriented. The flow starting from this point(RTL code) till it gets manufactured in to a chip is called VLSI Backend flow. It involves multiple stages(Synthesis, DFT, Physical Design, STA, Custom Layout, Physical Verification, Fabrication and Post Silicon validation). VLSI Front end domain is more programming oriented and VLSI Back end is more tool and VLSI technology oriented. As shown above, every domain offers job opportunities. Even though Functional verification and Physical design offers more opportunities, they also have more people undergoing training. Hence student should choose domain of training based on interest rather than job openings.
RTL Design, RTL integration, Functional verification, formal verification is more focused on understanding design specification, learning bus protocols and implementing designs and testbenches based on these protocols using Verilog, SV & UVM. Job role is more programming oriented.
Rest of the flow (from Synthesis toll Post silicon validation), also called post-synthesis flow does not involve much of programming. These jobs are more EDA tool usage oriented. Engineer need to learn various aspects of the flow and learn required commands in tool to implement these steps. It may involve learning 100’s of tool commands and their significance to the VLSI implementation flow. The overall flow is implemented using TCL commands(above tool commands), so it will TCL exposure. It also requires good fundamentals of CMOS, FinFET, 2nd order effects, timing closure and digital design.
Student doesn’t need to learn all the aspects of VLSI flow. Choose one domain and get complete expertise in that topic.
When a student joins institute, we do not make any assumption on their current preparation level, all the training starts from basics.
Institute tied up with multiple VLSI companies. Student will get opportunity to attend these companies interviews. Support will be till the time student gets the job.
Yes. It is possible to get job in VLSI even with few years gap. We will provide you with required support and guidance.
Yes. 2 Years is short span, so with right set of projects and right skill set, you will find opportunities in VLSI
For a fresher salary can be anywhere from 2.5 Lakhs to 6 Lakhs. Product companies do offer up to 15 Lakhs, but they mostly hire from campus.
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I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
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