FPGA System Design training is a 6 months course provides participants with wider and deep understanding of the FPGA Architecture, Design, Timing closure flow and debugging.
FPGA System Design course is for both Design and verification engineers who want to gain expertise and hands on exposure to FPGA design, prototyping and Validation. FPGA training focuses on the subtleties of the Vivado flow and its add-on tools. By mastering the design methodologies presented in FPGA System Design course, participants will be able to close the timing of their designs faster, and also shorten the development time, and lower development costs.
Course combines insightful lectures with practical lab exercises to reinforce key concepts. FPGA training will also help experienced engineers working in other domains, planning to switch in to FPGA domain. Course provides multiple hands on project exposure to provide hands on exposure to the complete FPGA system design flow.
Course has been framed with a seamless interest to plug and play the FPGA boards. Every session is planned with good hands-on examples to enable quicker understanding. Lab sessions are planned at regular intervals. Traditional FPGA developers code in languages such as Verilog HDL and VHDL. These developers are comfortable with creating FPGAs using the software, closing timing on complicated hardware circuits and managing complicated I/O interfaces to the FPGA. Below is the quick review of the course.
- FPGA Architecture
- FPGA internals and I/0
- FPGA timing closure
- FPGA implementation by RTL mode as well as IP Mode
- FPGA debugging
- Software development kit environment
- Booting FPGA in petalinux/ubuntu
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- Custom layout
- Post silicon validation
Advanced Digital Design concepts
- Digital Design basics
- combinational logic
- sequential logic, FF, latch, counters
- Refer to Advanced digital design training page for detailed course contents
SOC Design and Verification concepts
- SOC Architecture overview
- SOC design concepts
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC Test Case coding
- SOC verification differences with module verification
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
Verilog for Design and verification
- Verilog language constructs
- Verilog design coding examples covering more than 20 standard designs
FPGA Design and FPGA design Flow
- PAL, CPLD and FPGA basics
- FPGA Design Flow
- Internals of FPGA and CPLD
- Logic implementation
- FPGA Architectures of various FPGA vendors
- Anti-fuse and SRAMS
- Logic elements and Look-up Tables
- Dedicated multipliers
- Distributed RAM
- Shift registers
- Virtex Architectures
- Introduction and usage of IP cores·
FPGA Simulation and Synthesis Tool Flow
- Modelsim/Icarus Verilog simulation
- Design Synthesis
FPGA Implementation Design Flow
- Design constraining and pin locking
- Timing analysis
- slack calculation
- Data loss due to large skew
- Maximum skew calculations with examples
- Period constraints
- Area and Power Constraints
- Static Timing Analysis
- FPGA programming
- Floor plan
- Place and Route
- Post map and Post P&R simulation
- XDC constraints
- Reading and analysing reports-post synthesis
- Post map simulation
- Post P·&R simulation
- Configuring FPGAs
- FSM Extraction
Timing Simulation and Programming
- Timing Simulation using Modelsim/Icarusverilog
- Programming using JTAG
System Level testing and debugging
- Debugging techniques
- Debugging using chip scope and Logic analyzers
- Protocols on FPGA
- High Speed SERDES
- Identification of the issues/resolving
FPGA SDK environment
- FPGA SDK environment
- FPGA Device selection
- PERL Interpreter
- File management
- Regular expressions
- Object oriented PERL
- PERL modules
Soft Skill Training
- Facing interviews effectively
- industry work culture
- Group discussions
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.
|Course||FPGA Design & Verification Course|
|Freshers||Full week course|
|Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students.|
|Weekdays sessions will be focused on course labs.|
|Students also get support on complete project flow during weekdays as well.|
|Working professionals||Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US)|
|8:30AM – 12:30PM (Theory session offered by trainer)|
|1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.|
|Students will take the weekday tests and assignments from home.|
|New batch starts||Every 8 Weeks|
|Tool||Questasim, Vivado, Zed board|
|Mode of training||Live online training|
|Course is also offered in elearning mode for self paced learning|
|Tool Access||Tool access for complete course duration|
After completing this training, you will know how to:
- Utilisation of the primary 7 series FPGA architecture resources
- Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyse designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
- Synthesize and implement an HDL design
- Utilise the available synthesis and implementation reports to analyse a design (utilisation, timing, power, etc.)
- Build custom IP with the IP Library utility
- Make basic timing constraints
- Describe and analyse common STA reports
- Identify synchronous design techniques
- Describe how an FPGA is configured
PROJECTS & LABS
- Lab 1: Vivado IDE – create a simple HDL design and simulate the design using the HDL simulator available in Vivado design suite. Generate the bit stream and debug the design using Vivado Logic Analyzer.
- FPGA simulation and generating the bit stream of combinational and sequential circuits, memories, and registers through the Vivado IDE
- FPGA design of Synchronous and Asynchronous FIFO.
- FPGA design of a I2C protocol
- FPGA design of a SPI protocol
- Lab2:Vivado IP integrator. Vivado project and use IP Integrator to develop a basic embedded system for a target board.Extending the Embedded System into Programmable Logic
- a. Adding Peripherals in Programmable Logic. Extend the hardware system by adding AXI peripherals from the IP catalog. Adding Your Own IP Peripheral
- Lab 3: Creating and Adding Your Own Custom IP.Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.
- Lab 4: Software Development Environment. Writing Basic Software Applications. Write a basic C application to access the peripherals.
- Lab 5: Software Development and Debugging Software Debugging Using SDK.Use API to drive CPU’s timer. Perform software debugging using SDK.
- Lab 6: Debugging using Chip scope-Vivado Logic Analyzer cores insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
- Lab7.Software Application Discussion about the Possible Applications using Zynq AP SOC
- Lab 8.Installing and running Linux. Installing Petalinux and Booting
Board used in the course
- ZYNQ Processor
- 667 MHz dual-core Cortex-A9 processor
- DDR3L memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
- High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
- Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C
- Programmable from JTAG, Quad-SPI flash, and microSD card
- Programmable logic equivalent to Artix-7 FPGA
- 1 GB DDR3L with 32-bit bus @ 1066 MHz
- 16 MB Quad-SPI Flash with factory programmed 128-bit random number and 48-bit globally unique EUI-48/64™ compatible identifier
- microSD slot
- Powered from USB or any 5V external power source
- USB and Ethernet
- Gigabit Ethernet PHY
- USB-JTAG Programming circuitry
- USB-UART bridge
- USB 2.0 OTG PHY with host and device support
- Audio and Video
- Pcam camera connector with MIPI CSI-2 support
- HDMI sink port (input) with CEC (Zybo Z7-20) and without CEC (Zybo Z7-10)
- HDMI source port (output) with CEC
- Audio codec with stereo headphone, stereo line-in, and microphone jacks
- Switches, Push-buttons, and LEDs
- 6 push-buttons (2 processor connected)
- 4 slide switches
- 5 LEDs (1 processor connected)
- 2 RGB LEDs (Zybo Z7-20) and 1 RGB LED (Zybo Z7-10)
- Expansion Connectors
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
- 8 Total Processor I/O
- 40 Total FPGA I/O (Zybo Z7-20) and 32 (Zybo Z7-10)
- 4 Analog capable 0-1.0V differential pairs to XADC
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
Zynq FPGA finds extensive applications in the following.
- Automotive applications
- Computer architecture
- Embedded Linux OS development
- Embedded processing systems
- Hardware/software co-design.
- Build and include hardware accelerators to meet bandwidth demanding applications
Does course practical sessions?
- Each aspect of course is supported by a lot of hands on exercises and lab.
- FPGA timing as well as prototyping.
- FPGA validation and debugging.
- Dedicated lab sessions with the tool as well as the hardware boards.
What are the Course Prerequisites?
- Expertise to C programming
- Exposure to Digital design basics
My college curriculum covers most of these topics, why should I opt for this course?
Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Support post course completion?
- Student can continue to work from institute till he/she gets job
- Student has option to repeat the course as required
- Option to meet trainer in person to clarify doubts
- Multiple trainers with 10 years of average experience of working in Functional Verification domain across mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
- Experience of working on multiple complex module level projects