UVM for Functional Verification course (VG-UVM) course is a 8 weeks course structured to enable engineers develop skills in full breadth of UVM features in complex testbench development.
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9,182 (Student Enrolled)
Trainer
Verification Methodologies: UVM & OVM
AHB UVC Development
AHB Interconnect Functional Verification
USB2.0 Register Layer
Course Assignments
Below is the list of projects student will be doing as part of 7 weeks training. Institute provides guidance(trainer will be doing all these projects) on all these projects. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
AHB UVC Development
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
Responsibilities:
APB UVC Development
APB is an AMBA protocol used for low performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various APB features.
Responsibilities:
Functional verification of AHB Interconnect using SV & UVM
AHB Interconnect is a configurable design used for connecting multiple AHB based masters to various AHB slaves. Design can be configured can multiple masters and multiple slaves. I was part of the team responsible for AHB interconnect functional verification. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various APB features.
Responsibilities:
Register model development for USB2.0 core
USB2.0 core is design used for interfacing USB controller with USB2.0 based function. Design consist of multiple registers to implement endpoint and other configuration requirements. I was responsible for developing Register model for USB2.0 registers.
Please note: this project does not involve USB2.0 verification. It only gives student with exposure to Register model development.
Course | UVM Training in Functional Verification |
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Duration | 8 weeks |
Next Batch | 10/December To enrol for UVM eLearning course for self paced learning. |
Schedule | Both Saturday & Sunday (8:30AM – 3:30PM IST) |
8:30AM to 12:30PM (Trainer led sessions covering theory and labs) | |
1PM to 5PM (Mentor guided sessions covering labs assignments and doubt clarifications). Online students from US will get support in different time. | |
Course repeats | Every 16 Weeks |
Tool | Questasim & VCS |
Mode of training | Classroom training |
Online training using live training sessions | |
Tool Access | Tool access for complete course duration |
Batch Size | 20 |
Assignments | 16 |
Trainer | 14+ Years experience in Functional verification |
UVM Material | Access |
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Course material | Shared over google drive consists of UVM userguide-Labs & project codes for AHB & AHB Interconnect |
Course page access | Get login details from Admin |
Assignments-Checklist-Session notes | Course page |
Labs | Shared as part of course material |
Tool access | VPN |
Tool usage video | Youtube video shared as part of course guidelines |
Gvim install & usage | Youtube video shared as part of course guidelines |
How to run UVM TB using questasim | Youtube video shared as part of course guidelines |
How to use course material | Share as part of Course material |
Resume update | Share as part of Course material |
Session Notes | Uploaded to the course page |
Interview Questions | Uploaded to course page |
Labs for every week session | sent as mail attachment at the end of every week |
Students enrolled for the course(Log in to youtube using gmail Id to view below videos): |
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Click here to view how to run UVM TB using Questasim video |
Click here to view Questasim usage video |
Click here to view VCS Usage video |
Click here to view GVIM editor video |
Student will get access to UVM assignments, labs, session notes, interview questions, and sample resumes on course page.
What are the Course Prerequisites?
Does course cover practical sessions on UVM usage?
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
Do you offer support after course completion?
Trainer Profile
Teacher is an important part of anybody's education.
I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.
I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.