UVM for Functional Verification course (VG-UVM) course is a 8 weeks course structured to enable engineers develop skills in full breadth of UVM features in complex testbench development. UVM course is targeted towards engineers looking to explore functional verification techniques involving advanced methodology concepts like factory, databases and register layer. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. UVM course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex test bench development coding, to ensure a smooth learning curve.
UVM course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AHB, APB), UVC development for these protocols and multiple industry standard projects with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
UVM constructs are learnt using more than 100+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc. AHB Interconnect design is used as a reference example to learn all above aspects of UVM. These examples cover more than 90% of questions asked in VLSI interviews.
UVM course also covers multiple hands-on verification projects based on AHB, APB, and AHB Interconnect. Learning starts from simple projects like AHB UVC development to complex design verification projects involving Functional verification of AHB Interconnect using SV & UVM. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.
UVM course also involves 16 detailed assignments. Student will be provided with guidance in solving these assignments. Student progress is tracked using completion of assignments as a sole criteria. Student is offered with multiple interview opportunities based on performance in assignments.
Below is salient features of UVM for Functional Verification training course.
- UVM language constructs learning using 100+ detailed examples
- UVC development for AHB and APB protocols
- AHB Interconnect model verification
- USB2.0 register model development
- 16 detailed assignments covering all aspects of UVM
Verification Methodologies: UVM & OVM
- AHB Interconnect verification project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- AHB Protocol and AHB UVC development
- Coding from scratch with detailed explanation of each aspect.
- Setting up a highly configurable UVC to meet different TB requirements.
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Different types of sequences used in test benches
- Reset sequence
- Power up sequence
- interrupt handling sequence
- DMA handling sequence
- FSM verification sequence
- Layered sequence development
- How to create multiple layers of sequences
- Creating complex test cases using layered sequences
- Virtual sequence library
- Creating test cases using virtual sequence library
- Synchronization classes
- uvm_barrier
- uvm_event
- Container classes
- Policy classes
- uvm_printer
- uvm_recorder
- uvm_packer
- uvm_comparer
- Comparators
- In order comparator
- Algorithmic comparator
- TLM2.0
- Blocking transport
- Non-blocking transport
- Register Layer development for USB2.0 core
- Note: Doesn’t involve USB2.0 core verification
- Connecting multiple UVCs
- How to setup a complex testbench environment with multiple UVC’s connected.
- uvm_heartbeat
- How to check test bench status using heartbeat
- uvm_report_catcher
- How to handle error testcases using report catcher
- Phase jumping
- uvm_domain
AHB UVC Development
- AHB Protocol
- AHB System architecture
- Features
- Signals
- Timing Diagrams
- AHB UVC Architecture
- AHB UVC Component Coding
- AHB UVC Sequence & Test Development
AHB Interconnect Functional Verification
- AHB Interconnect Testbench Architecture
- AHB UVC & APB UVC in Interconnect Testbench setup
- Verification Component Coding
- Testcase & virtual sequence Development & Debug
USB2.0 Register Layer
- Listing down registers
- Creating Register Model
- Integrating Register Model in to Testbench
- Using Register Model to create tests
- Using Register Model in scoreboard
Course Assignments
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
Below is the list of projects student will be doing as part of 7 weeks training. Institute provides guidance(trainer will be doing all these projects) on all these projects. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
- majority of standard protocols(AHB and APB etc)
- Industry standard simulation tools like Questasim & VCS
- Develop debug expertise
- UVM based TB development for complex Designs
AHB UVC Development
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
Responsibilities:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
APB UVC Development
APB is an AMBA protocol used for low performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various APB features.
Responsibilities:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down APB features and develop testplan for validating UVC
- Develop UVC components
- Integrated APB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
Functional verification of AHB Interconnect using SV & UVM
AHB Interconnect is a configurable design used for connecting multiple AHB based masters to various AHB slaves. Design can be configured can multiple masters and multiple slaves. I was part of the team responsible for AHB interconnect functional verification. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various APB features.
Responsibilities:
- Develop TB Architecture to be compatible with configurable number of master and slaves
- List down design features and develop testplan
- Develop and integrate TB components. AHB UVC developed was used in setting up TB.
- Integrate APB UVC at design configuration interface
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of functional verification using coverage criteria
Register model development for USB2.0 core
USB2.0 core is design used for interfacing USB controller with USB2.0 based function. Design consist of multiple registers to implement endpoint and other configuration requirements. I was responsible for developing Register model for USB2.0 registers.
- List down registers, their fields and various attributes
- Develop register model using UVM Register layer base classes.
Please note: this project does not involve USB2.0 verification. It only gives student with exposure to Register model development.
| Course | UVM Training in Functional Verification |
|---|---|
| Duration | 8 weeks |
| Next Batch | 22/July To enrol for UVM eLearning course for self paced learning. |
| Schedule | Both Saturday & Sunday (8:30AM – 3:30PM IST) |
| 8:30AM to 12:30PM (Trainer led sessions covering theory and labs) | |
| 1PM to 5PM (Mentor guided sessions covering labs assignments and doubt clarifications). Online students from US will get support in different time. | |
| Course repeats | Every 16 Weeks |
| Tool | Questasim & VCS |
| Mode of training | Classroom training |
| Online training using live training sessions | |
| Tool Access | Tool access for complete course duration |
| Batch Size | 20 |
| Assignments | 16 |
| Trainer | 14+ Years experience in Functional verification |
What are the Course Prerequisites?
- Expertise on SystemVerilog Language
- Exposure to Testbench coding using SystemVerilog
Does course cover practical sessions on UVM usage?
- Each aspect of course is supported by lot of practical examples
- AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
- All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
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UVM Material Access Course material Shared over google drive consists of UVM userguide-Labs & project codes for AHB & AHB Interconnect Course page access Get login details from Admin Assignments-Checklist-Session notes Course page Labs Shared as part of course material Tool access VPN Tool usage video Youtube video shared as part of course guidelines Gvim install & usage Youtube video shared as part of course guidelines How to run UVM TB using questasim Youtube video shared as part of course guidelines How to use course material Share as part of Course material Resume update Share as part of Course material Session Notes Uploaded to the course page Interview Questions Uploaded to course page Labs for every week session sent as mail attachment at the end of every week Students enrolled for the course(Log in to youtube using gmail Id to view below videos): Click here to view how to run UVM TB using Questasim video Click here to view Questasim usage video Click here to view VCS Usage video Click here to view GVIM editor video Student will get access to UVM assignments, labs, session notes, interview questions, and sample resumes on course page.
Trainer Profile
- 14+ years experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
- Fee: INR 14,000 + GST
- Confirm your course enrolment by making 5,000 INR transfer to below account.
