• VHDL Language constructs
  • Fundamental VHDL units
  • Library Declaration
  • Entity Declaration
  • Architecture Declaration
  • Data types
  • Basic TextIO
  • Primitive programming
  • Data flow programing
  • Signals & Variables, State machines
  • Memory Designing
  • Structural programming
  • Function & Procedure
  • Hierarchical Designs
  • Parameterized Design entities
  • Procedural Testbenches
• Labs based on simple design examples like FIFO, Dual port RAM, FSM’s, etc

Course Overview

• 5 weeks training
• 8 hours per week (2 sessions on Saturday & Sunday, 4 Hours each)
• Fee live Training: 10,000
• E-learning Fee :6,000
• Next Batch: Adhoc

Experienced Trainer

• 12+ year’s exp. in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.