Advanced Physical Design Training

Advanced Physical Design Training is a 4 months course meant for working professionals to gain in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including all the aspects of Physical design flow at 14nm.



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Course Overview

Advanced Physical Design Training is a 4 months course meant for working professionals to gain in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including all the aspects of Physical design flow at 14nm. Course assumes that student is familiar with fundamental concepts of Physical design like CMOS, Digital design and fabrication. Course involves multiple hands on projects using Synopsys tools(DC, ICC II, Star RC, PT, ICV). Synopsys flow is among widely used PnR flow in industry.

Physical Design training emphasizes on issues faced in industry level projects and how to resolve those issues. Training also focus on other aspects of VLSI back end flow including Synthesis, IR drop analysis and Physical verification. Training will provide participants with expertise on entire back end flow, making sure that candidate fits in to various job requirements.

Advanced Physical design course syllabus (Duration: 4 months)

  • Basics of Synthesis
  • High Level Synthesis Flow
  • Reading of Verilog RTL File
  • Target and Link Libraries
  • Resolving References with Link Libraries
  • Reading hierarchical Designs
  • Reading ddc design
  • Analyse & Elaborate Commands
  • Constraining and Compiling RTL
  • Post Synthesis Output Data
  • Constraining Register to Register Paths
  • Constraining Inputs Paths
  • Constraining Outputs Paths
  • Virtual Clock
  • Load Budgeting
  • Default Path Groups
  • Creating User-defined Path Groups
  • Prioritizing Path Groups
  • Timing Reports
  • Analyzing Timing Reports
  • Defining a Clock with additional options
  • Input Delay with additional options
  • Output Delay with additional options
  • Pre-CTS versus Post CTS Clock Latencies
  • Independent IO Latencies
  • Output Delay with Network Latency
  • Output Delay with Source Latency
  • Different IO versus Internal Latencies
  • IO Clock Latencies
  • Handling Different IO Vs Internal Latencies
  • Virtual External Clock Latencies
  • Included External Clock Latencies
  • Multiple Synchronous Clocks
  • Multiple Clocks Input Delay
  • Maximum Internal Input Delay
  • Multiple Clock Output Delay
  • Maximum Internal Output Delay
  • Inter Clock Uncertainty
  • Generated Clocks
  • Mutual Exclusive Synchronous Clocks
  • Logically Exclusive Clocks
  • Multiple Clocks per Register
  • Cross Talk Analysis
  • Asynchronous Clocks
  • Multi Cycle Paths and Constraints
  • High Level Multi-Voltage Design Concepts
  • Supplies and Power Domains
  • Power Ports and Nets
  • Level Shifters
  • Power States and PS Table
  • IC Compiler II Library Manager
  • ICC Compiler II NDM Cell Library
  • Cell Library Characteristics
  • Library Manager Flow
  • Tech Only NDM Library
  • Technology-Only Library Flow
  • Technology File
  • Read TLU+ Files
  • Tech Library Preparation
  • Top Level, Sub-System Level and Block Level Design Setup
  • Set up initial Design Implementation
  • Loading Netlist from Synthesis
  • Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
  • Flow Setup and Design Setup
  • Loop-back to Synthesis for Correlation issues correction
  • Initial Floorplanning settings
  • Define Pad Instances (Physical Cells)
  • Pad Instance co-ordinates
  • Start Floorplaning
  • Core Die Size setting
  • Floorplanning of Pad Instances
  • Pad Filler Insertion
  • Define Pad Ring Power Grid
  • Macro Instance constraints
  • Macro Instance Array creation
  • Macro Instance Orientation
  • Anchor based and Relative Placement of Macro Instances
  • Macro Instance-Channel settings
  • Macro Instance placement – Manual
  • Congestion probability around Macro Instances
  • Defining Placement Blockages
  • Running placement
  • Defining placement strategies
  • In Place Optimization
  • Hierarchical Placement
  • Relative Placement
  • Congestion analysis and reduction
  • Macro placement changes to reduce congestion
  • Standard Cell Placement Constraints
  • Halo creation for instances
  • Congestion Analysis with Standard Cell placement
  • Local Congestion Reduction
  • Density Screen and Placement Blockage for Standard Cells
  • Congestion Aware Placement
  • Re-Check Macro Placement for better Congestion relief
  • Create Balanced Buffer Trees for High Fanout Net
  • Defining Power Structure
  • Logical Power/Ground Connections
  • Setting Power Network Constraints
  • Create and Analyze Power Structure
  • Change Power Constraints and Re-Createto meet IR requirements
  • Power Ground Pin connection and create Power Rails
  • Power Network Checks for IR and Resistance
  • Placement Blockage for Power Network
  • Incremental Placement
  • Re-Order Scan connectivity within Chain
  • Re-Partition Scan connectivity across Chains
  • SCANDEF file based Scan Chain Re-Ordering
  • Congestion checks for Overflow again
  • RC extraction for Net Parasitics
  • Check Timing for Max Analysis
  • Run Timing/Congestion aware Placement
  • Logic Re-Structuring for Placement and Timing
  • Check Pre-CTS timing based on Global Routing and Detailed Placement
  • Setting Clock Constraints such as Target Skew Target Insertion Delay
  • Clock Root Attributes as Stop, Float and Exclude Pins
  • Building for Generated and Gated Clocks
  • Don’t Touch attribute on existing Clock Tree structure
  • Defining Clock Buffers and Inverters.
  • Set Clock Tree Timing DRCs.
  • Non-Default Clock Routing rules setting
  • Perform Clock Tree Synthesis and Clock Tree Optimization
  • Reduce Hold Violations in Data paths and Scan Paths
  • Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
  • Synchronous Clock Balancing
  • Cross-Clock Delay Balancing
  • Logical Hierarchy aware CTS
  • Max and Min Analysis and subsequent Optimization
  • Fixing Violations
  • CTS Optimization across other modes and PVT corners (MMMC)
  • Skew and Insertion Delay checks
  • Checking Crosstalk on Clock Network
  • Pre-Route check points
  • Routing fundamentals
  • Global Route
  • Detail Routing
  • Track Assignment and Route
  • Refining Detailed Route
  • Over the Macro routing
  • Non-Preferred Routing direction
  • Clock Net Routing
  • Initial Data path routing
  • Redundant VIA insertion setting
  • Post Detailed Route Optimization
  • Fixing DRC Violations
  • Post Detailed Route Delay Calculation Algorithms
  • Crosstalk Delay and Noise Analysis and Fix
  • Check Leakage Power Dissipation
  • VT Cell swap for power and timing trade-off
  • Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
  • Reduce Dynamic power
  • Meet Total Power target
  • Functional ECO
  • Timing ECO
  • Metal Only ECO using Spare Cells for base frozen designs
  • Projects covering detailed flow from Input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
    • One project completely guided by the trainer
    • Other project done by student with trainer guidance
  • Project based on multi voltage domain.
  • Antenna Rules and Fixes
  • Critical Area Analysis
  • Wire Spreading and widening
  • Setting minimum metal jog length
  • Filler Cell Insertion
  • Metal Fill
  • Timing Checks after Metal Fill
  • Parasitic Extraction for SignOff timing analysis
  • Export Netlist
  • Export GDSII
Course Physical Design Training
Duration 4 months
Course start date 11/December
9AM – 1PM (Theory session offered by trainer)
2PM – 6PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
Tools Synopsys ICC II, RedHawk, Primetime, StarRC, Design Compiler, ICV
Mode of training Classroom training & Live Online training
Tool Access 24×7 Tool access for complete course duration
Certificate Certificate of course completion issued
Batch Size 20
Assignments 20
Trainer 15+ Years of industrial experience
  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts
  • Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
  • VLSIGuru believes in creating an educational model that is affordable and sustainable in the long run. We have been running successfully since we started training in 2012 with 3500+ students trained so far. We take pride in the fact that, it is VLSIGuru which made other institutes also to offer courses in 30K to 50K range, otherwise it used to be much higher.
  • Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.
  • Good understanding VLSI Technology basics(CMOS, FinFET, etc)
  • Digital design concepts
  • Each session of course is recorded, missed session videos will be shared
  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Course Material Shared:

Physical Design Course Material Access
Assignments-Checklist-Session notes Course page
Labs Copy labs from /home/vlsiguru/PHYSICAL_DESIGN/TRAINER* Refer to README files in individual folders.
Tool User guide /home/vlsiguru/PHYSICAL_DESIGN/Docs
acroread File_name.pdf to open any document.
How to use course material Shared as part of Course material
Resume update Course page
Interview Questions Uploaded to course page

Experienced Trainer

Senior Teacher

4.9 Star Rating

5 Courses

  • Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 45nm to 7nm
  • Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma



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Course Highlights
  • paper-plus

    1-1 Dedicated Mentor Support

  • paper-plus

    24/7 Tool Access

  • paper-plus

    Multiple MOCK Interviews

  • airplay

    Industry Standard Projects

  • clipboard

    Resume Preparation

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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