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Physical Design Training

Physical Design Training – Enroll Now to Grab Best Price.

Physical Design Training is a 14 weeks course(+5 weeks for freshers covering Device basics, Digital Design concepts,  TCL, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow. It is among widely used PnR flow in industry. Synopsys ICC & Primetime are industry standard sign off tools for Physical design & STA(sign off: chip STA is closed only when project flow is run on these tools), given this; would you learn Synopsys tools or any other tools for Physical Design training?

Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (at least two) on Million Gate Design from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.

Know More about Physical Design Training

Physical Design Training is supported using 15+ assignments covering all aspects of physical design implementation concepts including practical aspects. These assignments cover 90% of questions asked in interviews. These will solved as part of course lectures. Student will have 6 months access to tool from date of course registration. Student has option to connect to servers from home using VPN.

VLSIGuru Institute is setup in 2012, helped 1000+ students find right opportunities. VLSIGuru offers most affordable Physical Design Training in Bangalore. Bachelors and Masters of Engineering Students fresh out of graduation and ASIC Design Engineers who are in other areas of Implementation spectrum such as Front-End Logic Synthesis or Front-End STA can take this Physical Design course to make themselves completely equipped and industry ready. Online Physical Design Training is offered for students based out of Bangalore.

 

Physical Design Training

  • Physical Design Training is a 14 weeks course (+5 weeks for freshers covering Device fundamentals, Timing concepts. advanced digital design, TCL, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow. It is among widely used PnR flow in industry.

    Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (at least two) on Million Gate Design from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.

    Physical Design Training is supported using 15+ assignments covering all aspects physical design implementation concepts as well as practical aspects. These assignments would cover more than 90% of questions asked in interviews. These assignments will solved as part of course lectures. Student will have 6 months access to tool from date of course registration. Student has option to connect to servers from home using VPN.

    VLSIGuru Institute is setup in 2012, helped 500+ students find right opportunities. VLSIGuru offers most affordable Physical Design Training in Bangalore. Bachelors and Masters of Engineering Students fresh out of graduation and ASIC Design Engineers who are in other areas of Implementation spectrum such as Front-End Logic Synthesis or Front-End STA can take this Physical Design course to make themselves completely equipped and industry ready. Online Physical Design Training is offered for students based out of Bangalore.

    Below are the Physical design Training topics.
    Netlist to GDSII flow :
    • Initial Design Setup
    • Floorplanning
    • Placement
    • Power Planning
    • Scan chain re-ordering and re-partitioning
    • Global Routing
    • Clock Tree Synthesis
    • Detailed Routing
    • Power Analysis (static and dynamic)
    • Engineering Change Order flow (eco)
    • Design For Manufacturability

    • VLSI Flow(PD Basics 5 weeks Course)

      • Specification
      • RTL coding, lint checks
      • RTL integration
      • Connectivity checks
      • Functional Verification
      • Synthesis & STA
      • Gate level simulations
      • Power aware simulations
      • Placement and Routing
      • DFT
      • Custom layout
      • Post silicon validation

    • Semiconductor device fundamentals(PD Basics 5 weeks Course)

      • Conductors, Semiconductors, Insulators
      • Diode
      • BJT (Current controlled transistors)
      • MOSFET (NMOS, PMOS, CMOS) (Voltage controlled transistors)
      • FinFET
      • Device Fabrication
      • Significance of above aspects with Physical Design flow

    • Advanced Digital Design concepts(PD Basics 5 weeks Course)

      • Digital Design basics
      • combinational logic
      • sequential logic, FF, latch, counters
      • Memories
      • Setup time, Hold time, timing closure, fixing setup time and hold time violations
      • STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations

    • UNIX(PD Basics 5 weeks course)

      • Shells
      • File and directory management
      • User administration
      • Environment variables
      • Commonly used commands
      • Shell scripting basics
      • SEd and AWK
      • Revision management
      • Makefiles

    • TCL Scripting(PD Basics 5 weeks course)

      • PERL Interpretor
      • Variables
      • File management
      • Subroutines
      • Regular expressions
      • Object oriented PERL

    • Initial Design Setup

      • Top Level, Sub-System Level and Block Level Design Setup
      • Set up initial Design Implementation
      • Loading Netlist from Synthesis
      • Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
      • Flow Setup and Design Setup
      • Loop-back to Synthesis for Correlation issues correction

    • FloorPlanning

      • Initial Floorplanning settings
      • Define Pad Instances (Physical Cells)
      • Pad Instance co-ordinates
      • Start Floorplaning
      • Core Die Size setting
      • Floorplanning of Pad Instances
      • Pad Filler Insertion
      • Define Pad Ring Power Grid
      • Macro Instance constraints
      • Macro Instance Array creation
      • Macro Instance Orientation
      • Anchor based and Relative Placement of Macro Instances
      • Macro Instance-Channel settings
      • Macro Instance placement - Manual
      • Congestion probability around Macro Instances
      • Defining Placement Blockages

    • Placement

      • Running placement
      • Defining placement strategies
      • In Place Optimization
      • Hierarchical Placement
      • Relative Placement
      • Congestion analysis and reduction
      • Macro placement changes to reduce congestion
      • Standard Cell Placement Constraints
      • Halo creation for instances
      • Congestion Analysis with Standard Cell placement
      • Local Congestion Reduction
      • Density Screen and Placement Blockage for Standard Cells
      • Congestion Aware Placement
      • Re-Check Macro Placement for better Congestion relief
      • Create Balanced Buffer Trees for High Fanout Net

    • Power Planning

      • Defining Power Structure
      • Logical Power/Ground Connections
      • Setting Power Network Constraints
      • Create and Analyze Power Structure
      • Change Power Constraints and Re-Createto meet IR requirements
      • Power Ground Pin connection and create Power Rails
      • Power Network Checks for IR and Resistance
      • Placement Blockage for Power Network
      • Incremental Placement

    • Scan Chain RE-Ordering and RE-Partitioning

      • Re-Order Scan connectivity within Chain
      • Re-Partition Scan connectivity across Chains
      • SCANDEF file based Scan Chain Re-Ordering

    • Global Routing

      • Congestion checks for Overflow again
      • RC extraction for Net Parasitics
      • Check Timing for Max Analysis
      • Run Timing/Congestion aware Placement
      • Logic Re-Structuring for Placement and Timing

    • Clock Tree Synthesis

      • Check Pre-CTS timing based on Global Routing and Detailed Placement
      • Setting Clock Constraints such as Target Skew Target Insertion Delay
      • Clock Root Attributes as Stop, Float and Exclude Pins
      • Building for Generated and Gated Clocks
      • Don't Touch attribute on existing Clock Tree structure
      • Defining Clock Buffers and Inverters.
      • Set Clock Tree Timing DRCs.
      • Non-Default Clock Routing rules setting
      • Perform Clock Tree Synthesis and Clock Tree Optimization
      • Reduce Hold Violations in Data paths and Scan Paths
      • Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
      • Synchronous Clock Balancing
      • Cross-Clock Delay Balancing
      • Logical Hierarchy aware CTS
      • Max and Min Analysis and subsequent Optimization
      • Fixing Violations
      • CTS Optimization across other modes and PVT corners (MMMC)
      • Skew and Insertion Delay checks
      • Checking Crosstalk on Clock Network

    • Detailed Routing

      • Pre-Route check points
      • Routing fundamentals
      • Global Route
      • Detail Routing
      • Track Assignment and Route
      • Refining Detailed Route
      • Over the Macro routing
      • Non-Preferred Routing direction
      • Clock Net Routing
      • Initial Data path routing
      • Redundant VIA insertion setting
      • Post Detailed Route Optimization
      • Fixing DRC Violations
      • Post Detailed Route Delay Calculation Algorithms
      • Crosstalk Delay and Noise Analysis and Fix

    • Power Analysis (Static and Dynamic)

      • Check Leakage Power Dissipation
      • VT Cell swap for power and timing trade-off
      • Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
      • Reduce Dynamic power
      • Meet Total Power target

    • Engineering Change Order Flow (ECO)

      • Functional ECO
      • Timing ECO
        • 1) Transition Fixes 2) Capacitance Fixes 3) Setup Fixes 4) Hold Fixes 5) Recovery/Removal Fixes 6) Clock Gating Checks
      • Metal Only ECO using Spare Cells for base frozen designs

    • Design For Manufacturability

      • Antenna Rules and Fixes
      • Critical Area Analysis
      • Wire Spreading and widening
      • Setting minimum metal jog length
      • Filler Cell Insertion
      • Metal Fill
      • Timing Checks after Metal Fill
      • Parasitic Extraction for SignOff timing analysis
      • Export Netlist
      • Export GDSII

    • Softskill Training

      • Facing interviews effectively
      • Industry work culture
      • Group discussions
  • Course Physical Design Training
    Duration 14 weeks(19 weeks for freshers)
    Next Batch 22/SEP
    Demo Session 22/SEP (8:30AM - 12:00PM)
    Registration 23/SEP
    Schedule
    Freshers Full week course
    Saturday & Sunday(8:30AM - 4:30PM India time. Monday to Friday(9:30AM to 12:30PM).
    Weekdays sessions will be focused on training on device fundamentals - Digital Design - UNIX and TCL scripting.
    Working professionals Saturday & Sunday(8:30AM - 4:30PM India time. Flexible timings for students attending online from US)
    8:30AM - 12:30PM (Theory session offered by trainer)
    1PM - 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
    Students will take the weekday tests and assignments from home.
    Students also get support on complete project flow during weekdays as well.
    New batch starts Every 4 Weeks
    Fee INR 34000 (All inclusive) (Classroom training)
    INR 42000 (All inclusive) (Online training)
    INR 5000 (All inclusive) (Course on Physical Design basics + TCL + Unix)
    Tool Synopsys IC compiler
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access at institute. VPN access to online students only(at extra cost; not part of course fee)
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 40
    Assignments 20
    Evaluation tests 70(student will take one evaluation test once every 2 days; followed by discussion on same).
    Admission criteria Student need to undergo evaluation test based on basic digital and aptitude
    Placement support Interview opportunity in at least 6 companies
    Trainer 15+ Years of industrial experience

    • Why course fee very less compared to other institutes?

      • Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
      • VLSIGuru believes in creating educational model which is affordable and, sustainable in the long run. It has been a success since we started training in 2012. Since then we have trained 2400+ students in VLSI alone. We estimate to train 1200 students in 2018.
      • Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.

    • What are the Course Prerequisites?

      • Good understanding VLSI Technology basics(CMOS, FinFET, etc)
      • Digital design concepts

    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared

    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year

    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Physical Design Course Material Access
    Course material Shared over google drive
    Course page access Get login details from Admin
    Assignments-Checklist-Session notes Course page
    Labs Copy labs from /home/vlsiguru/PHYSICAL_DESIGN/TRAINER* Refer to README files in individual folders.
    Tool User guide /home/vlsiguru/PHYSICAL_DESIGN/Docs
    acroread File_name.pdf to open any document.
    How to use course material Shared as part of Course material
    Resume update Course page
    Interview Questions Uploaded to course page
    Students enrolled for the course(Log in to youtube using gmail Id to view below videos):
    Click here to view Course Page access video
    Click here to view video on how to connect to VPN
    Click here to view video on how to invoke ICC - DC - Primetime
    Click here to view ICC usage video-1
    Click here to view ICC usage video-2

    Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
    Course PPTs (Only for registered students. Please login to website and then access the PPTs from this page)
    Unit1 : Data base setup & Design Checks Presentation
    Unit2 : Synthesis Presentation
    Unit3 : STA Presentation
    Unit4 : STA(Advanced) Presentation
    Unit5 : Floorplanning Presentation
    Unit6 : Placement Presentation
    Unit7 : Routing Presentation
    Unit8 : CTS Presentation
    Unit9 : SCAN Presentation
    Unit10 : Low Power Presentation
    Unit11 : Physical Verification Presentation
    Unit12 : IR-DROP Presentation
    • Engineers planning to make career in VLSI backend flow
    • Verification engineers planning to gain complete flow exposure
    • Engineering college faculty looking to enhance their VLSI skill set
    • Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 45nm to 7nm
    • Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma
Quality VLSI Training at Affordable Fee.

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