• Physical design basics course syllabus (Duration: 3 months)

• EDA Tools Used in Physical Design Flow

  PD Flow Stage	Synopsys Tool	Cadence Tool
  RTL to Gate Synthesis	Design Compiler (DC)	Genus
  Floorplanning & Placement	IC Compiler II (ICC2)	Innovus
  Power Planning	ICC2 / PrimePower	Innovus / Voltus
  Clock Tree Synthesis (CTS)	ICC2	Innovus
  Routing (Global + Detailed)	ICC2	Innovus
  Parasitic Extraction (PEX)	StarRC	Quantus QRC
  Timing Analysis (STA)	PrimeTime	Tempus
  Signal Integrity (SI)	PrimeTime SI / StarRC	Tempus SI / Quantus QRC
  Power Integrity (IR/EM)	RedHawk-SC (via ANSYS)	Voltus
  Formal Equivalence Checking	Formality	Conformal
  Physical Verification (DRC/LVS/ERC)	IC Validator (ICV)	Pegasus / PVS
  GDSII Generation	ICC2	Innovus

  VLSI Design flow

  • Specification
  • RTL coding, lint checks
  • RTL integration
  • Connectivity checks
  • Functional Verification
  • Synthesis & STA
  • Gate level simulations
  • Power aware simulations
  • Placement and Routing
  • DFT
  • Custom layout
  • Post silicon validation

  Semiconductor device fundamentals

  • Transistors in hardware design
  • Significance of transistors in hardware design
  • Logic gate implementation using BJT, CMOS
  • MOSFET functionality
  • Semiconductors
  • What makes Semiconductor special element?
  • Classification of solids into three types
  • Conductor, Insulator, Semiconductor
  • Energy bands in Solids
  • Types of Semiconductors
  • Intrinsic Semiconductors
  • Extrinsic Semiconductors
  • Types of Extrinsic Semiconductors
  • N-type Extrinsic Semiconductor
  • P-type Extrinsic Semiconductor
  • Si, Ge – comparison
  • Types of current in Semiconductors – Drift, Diffusion
  • ion
  • PN Junction dioda
  • PN Junction – forward, reverse bias
  • V-I Characteristics of PN Junction Diode
  • Different types of Diode
  • Applications of Diode
  • BJT
  • BJT
  • BJT working principle?
  • How BJT can be used for large scale manufacturing
  • BJT fabrication steps
  • Types of BJT?
  • Why BJT is not used in for lower technology nodes?
  • Issues with BJT?
  • Advantages of BJT?
  • NAND gate using BJT?
  • Field Effect Transistor : FET
  • What is Field Effect Transistor?
  • Types of FET
  • NMOS
  • PMOS
  • CMOS
  • Fin
  • NMOS
  • NMOS
  • What is NMOS?
  • NMOS working principle?
  • Different voltages, currents, their equations
  • NMOS circuit representation
  • How NMOS works like a switch
  • How NMOS can be used for large scale manufacturing
  • NMOS fabrication steps
  • Types of NMOS?
  • Why CMOS is used instead of NMOS?
  • Issues with NMOS?
  • Advantages of NMOS?
  • NAND gate using NMOS?
  • CMOS
  • CMOS
  • What is CMOS?
  • CMOS working principle?
  • Different voltages, currents, their equations
  • CMOS circuit representation
  • How CMOS works like a switch
  • How CMOS can be used for large scale manufacturing
  • CMOS fabrication steps
  • Types of CMOS?
  • Issues with CMOS?
  • Advantages of CMOS?
  • NAND gate using CMOS?
  • CMOS second order effects?
  • FinFET
  • FinFET
  • What is FinFET?
  • FinFET working principle?
  • Different voltages, currents, their equations
  • CMOS circuit representation
  • How CMOS works like a switch
  • How FinFET can be used for large scale manufacturing
  • FinFET fabrication steps
  • Types of FinFET?
  • Issues with FinFET?
  • Advantages of FinFET?
  • NAND gate using FinFET?
  • FinFET second order effects?

  IC fabrication

  • Layers of CMOS
  • Depositing oxide layer
  • Photolithography
  • Masking
  • Etching Layers
  • Formation of nwell
  • Self aligned gate fabrication process
  • Diffusion to create n+ and P+ regions
  • Metallization

  Advanced Digital Design

  • Combinational logic
  • Number systems
  • Radix conversions
  • K-maps, min-terms, max terms
  • Logic gates
  • Realization of logic gates using mux’s and universal gates
  • Compliments (1/2/9/10’s complement)
  • Arithmetic operations using compliments
  • Boolean expression minimization, Dmorgan theorems
  • POS and SOP
  • Conversion and realization
  • Adders
  • Half adder
  • Full adder
  • Subtractor
  • Half subtractor
  • Full subtractor
  • Multiplexers
  • Realizing bigger Mux’s using smaller Mux’s
  • Implementing Adders and subtractors using Multiplexers
  • Decoders and Encoders
  • Implementing Decoders and Encoders using Mux and Demux
  • Bigger Decoder/Encoder using smaller Decoder/Encoder
  • Comparators
  • Implementing multi bit Comparators using 1-bit Comparator
  • Sequential logic
  • Latch, Flipflop
  • Latch, Flipflop using Gates or Mux’s
  • Different types of FFs
  • FF Truth table
  • Excitation tables
  • Realization of FF’s using other FF’s
  • Applications of FF’s, Latches
  • Counters
  • Shift registers
  • Synchronizers for clock domain crossing
  • FSM’s
  • Mealy, Moore FSM
  • Different encoding styles
  • Frequency dividers
  • Frequency multiplication
  • STA
  • Setup time, Hold time, timing closure
  • fixing setup time and hold time violations
  • Launch flop, capture flop

  PD flow keywords and VLSI Technology concepts

  • Introduction to majorly used keywords on PD flow
  • VLSI Technology concepts
    • Resistance, Capacitance, Inductance
    • Parasitic capacitance
    • L-C-R circuit analysis
    • RC circuit significance with circuit delay
  • Clock distribution concepts, skew

  Linux commands – hands on training

  • Installing Linux platform in Windows
  • Linux basics
  • Linux versus Windows
  • Linux Terminal
  • File and Directory management
  • Changing file permissions
  • Absolute path and relative path
  • Working with directories
  • GVIM – major keyboard shortcuts
  • Text display commands
  • Root configuration files
  • Environment variables
  • Text processing commands
    • grep, fgrep
    • xargs
    • SEd
    • AWK
    • Pipes and filters
  • Connecting to server
  • Process management
  • LSF
  • Ping
  • FTP
  • CTAGs
  • File compress and extract
  • Soft links

  TCL scripting

  • Overview
  • Env Setup
  • Special Variables
  • Data Types
  • Variables
  • Operators
  • Decisions
  • Loops
  • Arrays, Strings, Lists, Dictionary
  • History and Redoing of commands
  • String Pattern Matching commands
• Physical design main course syllabus (Duration: 5 months)

• Synthesis

  • Basics of Synthesis
  • High Level Synthesis Flow
  • Reading of Verilog RTL File
  • Target and Link Libraries
  • Resolving References with Link Libraries
  • Reading hierarchical Designs
  • Reading ddc design
  • Analyse & Elaborate Commands
  • Constraining and Compiling RTL
  • Post Synthesis Output Data

  Timing Constraints

  • Constraining Register to Register Paths
  • Constraining Inputs Paths
  • Constraining Outputs Paths
  • Virtual Clock
  • Load Budgeting
  • Default Path Groups
  • Creating User-defined Path Groups
  • Prioritizing Path Groups
  • Timing Reports
  • Analyzing Timing Reports
  • Defining a Clock with additional options
  • Input Delay with additional options
  • Output Delay with additional options
  • Pre-CTS versus Post CTS Clock Latencies
  • Independent IO Latencies
  • Output Delay with Network Latency
  • Output Delay with Source Latency
  • Different IO versus Internal Latencies
  • IO Clock Latencies
  • Handling Different IO Vs Internal Latencies
  • Virtual External Clock Latencies
  • Included External Clock Latencies
  • Multiple Synchronous Clocks
  • Multiple Clocks Input Delay
  • Maximum Internal Input Delay
  • Multiple Clock Output Delay
  • Maximum Internal Output Delay
  • Inter Clock Uncertainty
  • Generated Clocks
  • Mutual Exclusive Synchronous Clocks
  • Logically Exclusive Clocks
  • Multiple Clocks per Register
  • Cross Talk Analysis
  • Asynchronous Clocks
  • Multi Cycle Paths and Constraints

  UPF

  • High Level Multi-Voltage Design Concepts
  • Supplies and Power Domains
  • Power Ports and Nets
  • Level Shifters
  • Power States and PS Table

  NDM Libraries

  • IC Compiler II Library Manager
  • ICC Compiler II NDM Cell Library
  • Cell Library Characteristics
  • Library Manager Flow
  • Tech Only NDM Library
  • Technology-Only Library Flow
  • Technology File
  • Read TLU+ Files
  • Tech Library Preparation

  Initial Design Setup

  • Top Level, Sub-System Level and Block Level Design Setup
  • Set up initial Design Implementation
  • Loading Netlist from Synthesis
  • Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
  • Flow Setup and Design Setup
  • Loop-back to Synthesis for Correlation issues correction

  Placement

  • Running placement
  • Defining placement strategies
  • In Place Optimization
  • Hierarchical Placement
  • Relative Placement
  • Congestion analysis and reduction
  • Macro placement changes to reduce congestion
  • Standard Cell Placement Constraints
  • Halo creation for instances
  • Congestion Analysis with Standard Cell placement
  • Local Congestion Reduction
  • Density Screen and Placement Blockage for Standard Cells
  • Congestion Aware Placement
  • Re-Check Macro Placement for better Congestion relief
  • Create Balanced Buffer Trees for High Fanout Net

  Power Planning

  • Defining Power Structure
  • Logical Power/Ground Connections
  • Setting Power Network Constraints
  • Create and Analyze Power Structure
  • Change Power Constraints and Re-Createto meet IR requirements
  • Power Ground Pin connection and create Power Rails
  • Power Network Checks for IR and Resistance
  • Placement Blockage for Power Network
  • Incremental Placement

  Scan Chain RE-Ordering and RE-Partitioning

  • Re-Order Scan connectivity within Chain
  • Re-Partition Scan connectivity across Chains
  • SCANDEF file based Scan Chain Re-Ordering

  Floor Planning

  • Initial Floorplanning settings
  • Define Pad Instances (Physical Cells)
  • Pad Instance co-ordinates
  • Start Floorplaning
  • Core Die Size setting
  • Floorplanning of Pad Instances
  • Pad Filler Insertion
  • Define Pad Ring Power Grid
  • Macro Instance constraints
  • Macro Instance Array creation
  • Macro Instance Orientation
  • Anchor based and Relative Placement of Macro Instances
  • Macro Instance-Channel settings
  • Macro Instance placement – Manual
  • Congestion probability around Macro Instances
  • Defining Placement Blockages

  Global Routing

  • Congestion checks for Overflow again
  • RC extraction for Net Parasitics
  • Check Timing for Max Analysis
  • Run Timing/Congestion aware Placement
  • Logic Re-Structuring for Placement and Timing

  Clock Tree Synthesis

  • Check Pre-CTS timing based on Global Routing and Detailed Placement
  • Setting Clock Constraints such as Target Skew Target Insertion Delay
  • Clock Root Attributes as Stop, Float and Exclude Pins
  • Building for Generated and Gated Clocks
  • Don’t Touch attribute on existing Clock Tree structure
  • Defining Clock Buffers and Inverters.
  • Set Clock Tree Timing DRCs.
  • Non-Default Clock Routing rules setting
  • Perform Clock Tree Synthesis and Clock Tree Optimization
  • Reduce Hold Violations in Data paths and Scan Paths
  • Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
  • Synchronous Clock Balancing
  • Cross-Clock Delay Balancing
  • Logical Hierarchy aware CTS
  • Max and Min Analysis and subsequent Optimization
  • Fixing Violations
  • CTS Optimization across other modes and PVT corners (MMMC)
  • Skew and Insertion Delay checks
  • Checking Crosstalk on Clock Network

  Detailed Routing

  • Pre-Route check points
  • Routing fundamentals
  • Global Route
  • Detail Routing
  • Track Assignment and Route
  • Refining Detailed Route
  • Over the Macro routing
  • Non-Preferred Routing direction
  • Clock Net Routing
  • Initial Data path routing
  • Redundant VIA insertion setting
  • Post Detailed Route Optimization
  • Fixing DRC Violations
  • Post Detailed Route Delay Calculation Algorithms
  • Crosstalk Delay and Noise Analysis and Fix

  Power Analysis (Static and Dynamic)

  • Check Leakage Power Dissipation
  • VT Cell swap for power and timing trade-off
  • Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
  • Reduce Dynamic power
  • Meet Total Power target

  Engineering Change Order Flow (ECO)

  • Functional ECO
  • Timing ECO
  • Metal Only ECO using Spare Cells for base frozen designs

  Multiple Industry standard Projects

  • Projects covering detailed flow from Input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
    • One project completely guided by the trainer
    • Other project done by student with trainer guidance
  • Project based on multi voltage domain.

  Design For Manufacturability

  • Antenna Rules and Fixes
  • Critical Area Analysis
  • Wire Spreading and widening
  • Setting minimum metal jog length
  • Filler Cell Insertion
  • Metal Fill
  • Timing Checks after Metal Fill
  • Parasitic Extraction for SignOff timing analysis
  • Export Netlist
  • Export GDSII

  Softskill Training

  • Facing interviews effectively
  • Industry work culture
  • Group discussions

Course is offered in 2 modes:

• Full week course (for freshers)
  
  • 9AM to 1PM on 6 days/week (Friday is break)
• Weekends only course (for working professionals)
  
  • 9AM to 5:30PM on both Saturday & Sunday
    
    • Session timings might differ for students from US and other times zones.

Multiple Trainer

• Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 14nm to 28nm
• Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma