Physical Design Training

Overview

RedHawk : Power Integrity, IR Drop and Reliability Analysis training included(Only institute to offer this).

Physical Design Training is a 4 months course (+2 months for freshers covering Device fundamentals, IC fabrication, timing concepts. advanced digital design, analog design basics, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow(DC, ICC II, Star RC, PT, ICV). It is among widely used PnR flow in industry.

Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (Block level and Full chip level) from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.

Physical Design Training is supported using 15+ assignments covering all aspects physical design implementation flow including practical aspects. Assignments are detailed and well structured to cover all the aspects of Physical Design. These assignments will solved as part of course lectures. Student will have 12 months access to tool from date of course registration.

VLSIGuru Institute is setup in 2012, helped 1000+ students find right career opportunities. VLSIGuru offers affordable Physical Design Training in Bangalore and Noida. Course will Online Physical Design Training is offered for students based out of Bangalore.

Below are the Physical design Training topics.
Netlist to GDSII flow :

Initial Design Setup
Importing design
Floorplanning
Power Planning
Placement
Scan chain re-ordering and re-partitioning
Global Routing
Clock Tree Synthesis
Detailed Routing
Power Analysis (static and dynamic)
Engineering Change Order flow (ECO)
Design For Manufacturability

Syllabus

Physical design basics course syllabus (Duration: 2 months)

VLSI Design flow

Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation

Semiconductor device fundamentals

Conductors, Semiconductors, Insulators
Intrinsic and Extrinsic Semiconductors
Diode
BJT
MOSFET (NMOS, PMOS, CMOS)
FinFET
Device Fabrication
Significance of above aspects with Physical Design flow

Advanced Digital Design

Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Setup time, Hold time, timing closure, fixing setup time and hold time violations
STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
www.vlsiguru.com/digital-design-complete

Linux operating system

Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles

PD flow keywords and VLSI Technology concepts

Introduction to all the majorly used keywords on PD flow
VLSI Technology concepts
- Resistance, Capacitance, Inductance
- Parasitic capacitance
- L-C-R circuit analysis
- RC circuit significance with circuit delay
Clock distribution concepts, skew

TCL Scripting

Introduce TCL
Why TCL?
TCL Script Processing
Understand TCL uses and strengths
Writing simple TCL scripts
TCL for VLSI scripting
TCL : Main Features
TCL in EDA
TCL shell (tclsh)
Working with TCL scripts (UNIX)
TCL Interpreter in SoC Design Tools
TCL Scripting for SoC Design
TCL Commands
Variables
Substitution and Command Evaluation
Operators
Mathematical Functions
Procedures
Control flow : if, if-else, switch, for, foreach, while, break and continue
string, string operations
List, List manipulation
Arrays, array methods
Working with files
Command line arguments
Regular expressions
Complete TCL Scripts
TCL Packages

Physical design main course syllabus (Duration: 4 months)

Synthesis

Basics of Synthesis
High Level Synthesis Flow
Reading of Verilog RTL File
Target and Link Libraries
Resolving References with Link Libraries
Reading hierarchical Designs
Reading ddc design
Analyse & Elaborate Commands
Constraining and Compiling RTL
Post Synthesis Output Data

Timing Constraints

Constraining Register to Register Paths
Constraining Inputs Paths
Constraining Outputs Paths
Virtual Clock
Load Budgeting
Default Path Groups
Creating User-defined Path Groups
Prioritizing Path Groups
Timing Reports
Analyzing Timing Reports
Defining a Clock with additional options
Input Delay with additional options
Output Delay with additional options
Pre-CTS versus Post CTS Clock Latencies
Independent IO Latencies
Output Delay with Network Latency
Output Delay with Source Latency
Different IO versus Internal Latencies
IO Clock Latencies
Handling Different IO Vs Internal Latencies
Virtual External Clock Latencies
Included External Clock Latencies
Multiple Synchronous Clocks
Multiple Clocks Input Delay
Maximum Internal Input Delay
Multiple Clock Output Delay
Maximum Internal Output Delay
Inter Clock Uncertainty
Generated Clocks
Mutual Exclusive Synchronous Clocks
Logically Exclusive Clocks
Multiple Clocks per Register
Cross Talk Analysis
Asynchronous Clocks
Multi Cycle Paths and Constraints

UPF

High Level Multi-Voltage Design Concepts
Supplies and Power Domains
Power Ports and Nets
Level Shifters
Power States and PS Table

NDM Libraries

IC Compiler II Library Manager
ICC Compiler II NDM Cell Library
Cell Library Characteristics
Library Manager Flow
Tech Only NDM Library
Technology-Only Library Flow
Technology File
Read TLU+ Files
Tech Library Preparation

Initial Design Setup

Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction

FloorPlanning

Initial Floorplanning settings
Define Pad Instances (Physical Cells)
Pad Instance co-ordinates
Start Floorplaning
Core Die Size setting
Floorplanning of Pad Instances
Pad Filler Insertion
Define Pad Ring Power Grid
Macro Instance constraints
Macro Instance Array creation
Macro Instance Orientation
Anchor based and Relative Placement of Macro Instances
Macro Instance-Channel settings
Macro Instance placement – Manual
Congestion probability around Macro Instances
Defining Placement Blockages

Placement

Running placement
Defining placement strategies
In Place Optimization
Hierarchical Placement
Relative Placement
Congestion analysis and reduction
Macro placement changes to reduce congestion
Standard Cell Placement Constraints
Halo creation for instances
Congestion Analysis with Standard Cell placement
Local Congestion Reduction
Density Screen and Placement Blockage for Standard Cells
Congestion Aware Placement
Re-Check Macro Placement for better Congestion relief
Create Balanced Buffer Trees for High Fanout Net

Power Planning

Defining Power Structure
Logical Power/Ground Connections
Setting Power Network Constraints
Create and Analyze Power Structure
Change Power Constraints and Re-Createto meet IR requirements
Power Ground Pin connection and create Power Rails
Power Network Checks for IR and Resistance
Placement Blockage for Power Network
Incremental Placement

Scan Chain RE-Ordering and RE-Partitioning

Re-Order Scan connectivity within Chain
Re-Partition Scan connectivity across Chains
SCANDEF file based Scan Chain Re-Ordering

Global Routing

Congestion checks for Overflow again
RC extraction for Net Parasitics
Check Timing for Max Analysis
Run Timing/Congestion aware Placement
Logic Re-Structuring for Placement and Timing

Clock Tree Synthesis

Check Pre-CTS timing based on Global Routing and Detailed Placement
Setting Clock Constraints such as Target Skew Target Insertion Delay
Clock Root Attributes as Stop, Float and Exclude Pins
Building for Generated and Gated Clocks
Don’t Touch attribute on existing Clock Tree structure
Defining Clock Buffers and Inverters.
Set Clock Tree Timing DRCs.
Non-Default Clock Routing rules setting
Perform Clock Tree Synthesis and Clock Tree Optimization
Reduce Hold Violations in Data paths and Scan Paths
Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
Synchronous Clock Balancing
Cross-Clock Delay Balancing
Logical Hierarchy aware CTS
Max and Min Analysis and subsequent Optimization
Fixing Violations
CTS Optimization across other modes and PVT corners (MMMC)
Skew and Insertion Delay checks
Checking Crosstalk on Clock Network

Detailed Routing

Pre-Route check points
Routing fundamentals
Global Route
Detail Routing
Track Assignment and Route
Refining Detailed Route
Over the Macro routing
Non-Preferred Routing direction
Clock Net Routing
Initial Data path routing
Redundant VIA insertion setting
Post Detailed Route Optimization
Fixing DRC Violations
Post Detailed Route Delay Calculation Algorithms
Crosstalk Delay and Noise Analysis and Fix

Power Analysis (Static and Dynamic)

Check Leakage Power Dissipation
VT Cell swap for power and timing trade-off
Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
Reduce Dynamic power
Meet Total Power target

Engineering Change Order Flow (ECO)

Functional ECO
Timing ECO
Metal Only ECO using Spare Cells for base frozen designs

Multiple Industry standard Projects

2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
Projects based on multi voltage domain.
Student will be working on 3rd project independently with trainer/mentor support.

Design For Manufacturability

Antenna Rules and Fixes
Critical Area Analysis
Wire Spreading and widening
Setting minimum metal jog length
Filler Cell Insertion
Metal Fill
Timing Checks after Metal Fill
Parasitic Extraction for SignOff timing analysis
Export Netlist
Export GDSII

Softskill Training

Facing interviews effectively
Industry work culture
Group discussions

Schedule

Course is offered in 2 modes:

Full week course (for freshers)
- 9AM to 1PM on 6 days/week (Friday is break)
- Institute will be open from 8AM to 9PM on all the days. Student can practice and get mentor support during this time.
Weekends only course (for working professionals)
- 9AM to 5:30PM on both Saturday & Sunday
  - Session timings might differ for students from US and other times zones.
- Dedicated weekday online lab session support(on need basis)
Student may also opt for dedicated 30 hours of 1-1 mentor training sessions at an additional cost of 5,000 INR. (optional)
Session schedule

Course	Physical Design Training
Duration	4 months (6 months for freshers)
Course start date	29/May
Schedule
Freshers	Full week course
	All days except Friday (9AM – 1PM India time). This includes Saturday and Sunday.
	Weekdays sessions will be focused on training on CMOS, device fundamentals, Digital Design, Linux OS and TCL scripting for initial 8 weeks. Later 4 months, weekdays will be focused on project hands on labs.
Working professionals	Saturday & Sunday(9AM – 6PM India time. Flexible timings for students attending online from US)
	9AM – 1PM (Theory session offered by trainer)
	2PM – 6PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
	Students will take the weekday tests and assignments from home.
	Students also get support on complete project flow during weekdays as well.
New batch starts	Every 8 Weeks
Tools	Synopsys ICC II, RedHawk, Primetime, StarRC, Design Compiler, ICV
Mode of training	Classroom training
	Online training using live training sessions
Tool Access	Tool access for complete course duration
Certificate	Issued based on 50% assignment completion as criteria
Batch Size	20
Assignments	20
Evaluation tests	20(evaluation test followed by discussion on same).
Placement support	Institute does not give any commitment on job or number of opportunities, however student will be provided with opportunities till he/she gets job.
Trainer	15+ Years of industrial experience

Project Flow

FAQs

Do you offer support after course completion?

Yes, Course fee also includes support for doubt clarification sessions even after course completion
You have option to mail you queries
Option to meet in person to clarify doubts

Why course fee very less compared to other institutes?

Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
VLSIGuru believes in creating an educational model that is affordable and sustainable in the long run. We have been running successfully since we started training in 2012 with 3500+ students trained so far. We take pride in the fact that, it is VLSIGuru which made other institutes also to offer courses in 30K to 50K range, otherwise it used to be much higher.
Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.

What are the Course Prerequisites?

Good understanding VLSI Technology basics(CMOS, FinFET, etc)
Digital design concepts

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

Yes, You will have option to view the recorded videos of course for the sessions missed
You will have option to repeat the course any time in next 1 year

Course Material

Physical Design Course Material	Access
Assignments-Checklist-Session notes	Course page
Labs	Copy labs from /home/vlsiguru/PHYSICAL_DESIGN/TRAINER* Refer to README files in individual folders.
Tool User guide	/home/vlsiguru/PHYSICAL_DESIGN/Docs
	acroread File_name.pdf to open any document.
How to use course material	Shared as part of Course material
Resume update	Course page
Interview Questions	Uploaded to course page

Students enrolled for the course(Log in to youtube using gmail Id to view below videos):
Click here to view video on how to invoke ICC – DC – Primetime
Click here to view ICC usage video-1
Click here to view ICC usage video-2

Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.

Trainer

Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 45nm to 7nm
Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma

PD Basics and Main Course (24 weeks)	INR 45000 +GST
PD Main Course (17 weeks)	INR 37000 +GST

- Confirm your course enrolment by making 5,000 INR transfer to below account.
  - www.vlsiguru.com/fee-transfer/

Remaining fee can be paid in 2 instalments with gap of 1.5 months