DMA controller is a dual core design which support various transfers including memory to memory transfer, peripheral to memory transfer and peripheral to peripheral transfer. Design has 8 channels for concurrent transfers. Design also support command list for scatter and gather feature support. 

Course provides detailed exposure to complete project flow starting from reading the specification till coverage report generation and regression analysis. UVM based Test bench also includes register model development, integration, register access testcases, and functional test coding using register model. Student will get exposure to regression setup, coverage analysis and scoreboard development.

This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.