COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

For all courses:

  • GST is chargeable at 18% on top of the fee mentioned.
  • All courses offered in
  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when more than 5 students have registered for the course.
  • There is option to join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions. Beyond that student should join new batch.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 weeks of joining the course. There will not be any additional fee for switching to different course within 2 weeks.
  • Tool access for complete course duration for all relevant courses

Upcoming courses

CoursesStart DateLink
Embedded systems5/JuneCourse Structure
Verilog Training16/JulyCourse Structure
Physical Design Training17/JulyCourse Structure
Functional Verification course for experienced engineers16/JulyCourse Structure
Functional Verification Course for freshers16/JulyCourse Structure
FPGA design and verification training16/JulyCourse Structure
RTL design and integration training16/JulyCourse Structure
System Verilog functional verification Course16/JulyCourse Structure
Custom Layout Training17/JulyCourse Structure

Courses in VLSI Front End domain

CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
Functional Verification Training for FreshersVLSI Course Structure16/July28 weeks630005 weeks
Functional Verification Training for Experienced EngineersVLSI Course Structure16/July22 weeks500005 weeks
System Verilog TrainingSV Course Structure16/July7 weeks160005 weeks
VLSI InternshipVLSI Internship Structure16/July10 months630005 weeks
UVM TrainingUVM Course Structure16/July8 weeks195008 weeks
RTL Design and verification trainingCourse Structure16/July24 Weeks630005 weeks
FPGA Design and verification trainingCourse Structure16/July24 Weeks630005 weeks
Verilog TrainingVerilog Course Structure16/July8 Weeks150005 weeks
VHDL TrainingVHDL Course StructureAdhoc5 Weeks8000ad hoc

Courses in VLSI Backend

CourseCourse DetailsStart DateCourse DurationFeeNew Batch starts every
Physical Design TrainingCourse Structure17/July24 Weeks630008 weeks
RedHawk (Power Integrity & IR Drop Analysis) TrainingCourse StructureAdhoc5 Weeks1700012 weeks
Synthesis and STA TrainingCourse Structure17/July12 Weeks390008 weeks
DFT Trainingcourse structure17/July24 Weeks630008 weeks
Custom Layout & Physical Verification TrainingCourse structure17/July24 Weeks630008 weeks

Courses in Embedded Systems

CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
Embedded Systems TrainingEmbedded Systems Course Structure24/July18 Weeks390009 weeks

SoC & Courses on Standard Protocols

CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
ARM TrainingARM Architecture Training Course StructureAdhoc6 Weeks19000Adhoc
DDR Protocol TrainingDDR Training Course StructureAdhoc6 Weeks8000Adhoc
PCIe Protocol TrainingPCIe Training Course StructureAdhoc6 Weeks1100016 weeks
USB3.0 Protocol TrainingUSB30 Course StructureAdhoc6 Weeks1100016 weeks
GLS TrainingGLS Course StructureAdhoc3 Weeks700016 weeks
Low Power verification TrainingPower aware verification course structureAdhoc3 Weeks6000Adhoc
USB2.0 protocol and USB2.0 core verification TrainingUSB2.0 Course StructureAdhoc7 Weeks11000Adhoc
AMBA(AXI, AHB, APB) protocol and VIP & UVC development TrainingAMBA protocol training Course Structure07/MAY6 Weeks1500012 weeks
SoC Design & Verification TrainingSoC TrainingAdhoc6 Weeks15000Adhoc

Courses on Scripting Languages

CourseCourse DetailsStart DateCourse DurationFeeNew Batch starts every
PERL TrainingPERL Course Structureadhoc5 Weeks600010 weeks
Python TrainingPython Course Structureadhoc5 Weeks600010 weeks
TCL TrainingTCL Course StructureAdhoc6 Weeks900010 weeks
Shell TrainingSHELL Course StructureAdhoc4 Weeks450010 weeks

Call us for more details on VLSI Training course structure

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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