COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

For all courses:

  • GST is chargeable at 18% on top of the fee mentioned.
  • All Courses offered in
  • There is option to join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions. Beyond that student should join new batch.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 weeks of joining the course. There will not be any additional fee for switching to different course within 2 weeks.
  • Tool access for complete course duration for all relevant courses.
VLSIguru quality traning affordable fee in Bangalore

Upcoming courses

CoursesStart DateLink
Functional verification interview trainingAdhocCourse Structure
Physical design interview trainingAdhocCourse Structure

Courses in VLSI Front End domain

CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
Functional Verification Training for FreshersVLSI Course Structure05/October28 weeks630005 weeks
Functional Verification Training for Experienced EngineersVLSI Course Structure28/September22 weeks500005 weeks
System Verilog TrainingSV Course Structure28/September7 weeks160005 weeks
MTech Internship in VLSIMTech VLSI Internship Structure05/October10 months630005 weeks
MTech Internship in Embedded systemsMTech Embedded systems internship StructureAdhoc10 months630005 weeks
UVM TrainingUVM Course Structure05/October8 weeks195008 weeks
RTL Design and verification trainingCourse Structure05/October24 Weeks630005 weeks
FPGA Design and verification trainingCourse Structure05/October24 Weeks630005 weeks
Verilog TrainingVerilog Course Structure28/September8 Weeks150005 weeks
VHDL TrainingVHDL Course StructureAdhoc5 Weeks8000ad hoc

07

Courses in VLSI Backend

CourseCourse DetailsStart DateCourse DurationFeeNew Batch starts every
Physical Design TrainingCourse Structure06/October24 Weeks630008 weeks
RedHawk (Power Integrity & IR Drop Analysis) TrainingCourse StructureAdhoc5 Weeks1700012 weeks
Synthesis and STA TrainingCourse StructureAdhoc12 Weeks390008 weeks
DFT Trainingcourse structure05/October24 Weeks630008 weeks
Custom Layout & Physical Verification TrainingCourse structure06/October24 Weeks630008 weeks

Courses in Embedded Systems

CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
Embedded Systems TrainingEmbedded Systems Course StructureAdhoc18 Weeks390009 weeks

SoC & Courses on Standard Protocols

  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when
  •  more than 5 students have registered for the course.
CourseCourse DetailsStart DateCourse DurationFeesNew Batch starts every
ARM TrainingARM Architecture Training Course StructureAdhoc6 Weeks19000Adhoc
DDR Protocol TrainingDDR Training Course StructureAdhoc6 Weeks8000Adhoc
PCIe Protocol TrainingPCIe Training Course StructureAdhoc6 Weeks1100016 weeks
USB3.0 Protocol TrainingUSB30 Course StructureAdhoc6 Weeks1100016 weeks
GLS TrainingGLS Course StructureAdhoc3 Weeks700016 weeks
Low Power verification TrainingPower aware verification course structureAdhoc3 Weeks6000Adhoc
USB2.0 protocol and USB2.0 core verification TrainingUSB2.0 Course StructureAdhoc7 Weeks11000Adhoc
AMBA(AXI, AHB, APB) protocol and VIP & UVC development TrainingAMBA protocol training Course StructureAdhoc6 Weeks1500012 weeks
SoC Design & Verification TrainingSoC TrainingAdhoc6 Weeks15000Adhoc

Courses on Scripting Languages

CourseCourse DetailsStart DateCourse DurationFeeNew Batch starts every
PERL TrainingPERL Course Structureadhoc5 Weeks600010 weeks
Python TrainingPython Course Structureadhoc5 Weeks600010 weeks
TCL TrainingTCL Course StructureAdhoc6 Weeks900010 weeks
Shell TrainingSHELL Course StructureAdhoc4 Weeks450010 weeks

Call us for more details on VLSI Training course structure

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