COURSE SCHEDULE (VLSI, EMBEDDED SYSTEMS)

For all courses:

  • 18% GST applicable
  • All Courses offered in
  • Student can join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 months of joining the course with no additional fee.
VLSIguru quality traning affordable fee in Bangalore

Upcoming courses

Courses Start Date Link
Functional verification interview training Adhoc Course Structure
Physical design interview training Adhoc Course Structure

Courses in VLSI Front End domain

CourseStart DateCourse DurationFeeNew Batch starts every
Functional Verification Training for Freshers26/July28 weeks630005 weeks
Functional Verification Training for Experienced Engineers26/July22 weeks500005 weeks
System Verilog Training26/July7 weeks160005 weeks
MTech Internship in VLSI26/July10 months630005 weeks
MTech Internship in Embedded systemsAdhoc10 months630005 weeks
UVM Training26/July8 weeks195008 weeks
RTL Design and verification training26/July24 Weeks630005 weeks
FPGA Design and verification training26/July24 Weeks630005 weeks
Verilog Training26/July8 Weeks150005 weeks
VHDL TrainingAdhoc5 Weeks8000Adhoc

Courses in VLSI Backend DOMAIN

CourseStart DateCourse DurationFeeNew Batch starts every
Physical Design Training27/July24 Weeks630008 weeks
RedHawk (Power Integrity & IR Drop Analysis) TrainingAdhoc5 Weeks9000 
Synthesis and STA TrainingAdhoc12 Weeks390008 weeks
DFT Training27/July24 Weeks630008 weeks
Custom Layout & Physical Verification Training27/July24 Weeks630008 weeks

Courses in Embedded Systems

Course Start Date Course Duration Fees New Batch starts every
Embedded Systems Training Adhoc 18 Weeks 39000 9 weeks

Courses on SOC & Standard Protocols

  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when more than 5 students register for the course.

CourseStart DateCourse DurationFeesNew Batch starts every
ARM TrainingAdhoc6 Weeks19000Adhoc
DDR ProtocolAdhoc6 Weeks8000Adhoc
PCIe Gen5 protocolAdhoc6 Weeks1100016 weeks
USB3.2 protocolAdhoc6 Weeks1100016 weeks
Gate level simulations (GLS)Adhoc3 Weeks700016 weeks
Low Power verificationAdhoc3 Weeks6000Adhoc
USB2.0 protocol and USB2.0 core verificationAdhoc7 Weeks11000Adhoc
AMBA protocol and UVC developmentAdhoc6 Weeks1500012 weeks
AMBA CHIAdhoc6 Weeks90006 weeks
ACE ProtocolAdhoc6 Weeks40005 weeks
SoC Design & VerificationAdhoc6 Weeks15000Adhoc

Courses on Scripting Languages

Course Start Date Course Duration Fee New Batch starts every
PERL adhoc 5 Weeks 6000 10 weeks
Python adhoc 5 Weeks 6000 10 weeks
TCL Adhoc 6 Weeks 9000 10 weeks
Shell Adhoc 4 Weeks 4500 10 weeks

Call us for more details on VLSI Training course structure

Course Registration