For all courses:

  • Offered both in Classroom and Live online training mode.
  • Also offered in 1-1 training(charged per hour basis)
  • For any conflict in fee and start date with actual course page, this page has the accurate information.
  • Fee is all inclusive. What you see is what you pay. All the fee is in INR.
  • Fee for online course may differ from classroom course fee, please check the corresponding page for actual fee.
  • Student attending online training must connect to session using a system with webcam switched on.
  • Ad Hoc below refers to, courses where we do not get frequent requests, and are offered only when more than 5 students have registered for the course.
  • There is option to join ongoing batch within 2 weeks from course start date, we help cover up the missed sessions. Beyond that student can join new batch.
  • Students joining Design verification, Physical Design, DFT and Custom layout courses, will have option to switch to any other course within 2 weeks of joining the course. There will not be any additional fee for switching to different course within 2 weeks.
  • Tool access will be provided for 1 year at institute with no additional cost.
  • Fee refund policy: Fee is refunded on pro-rata basis, there will be 5% standard deduction.

Upcoming courses

Courses Start Date & Demo Class Link
Verilog Training  26/Oct (9AM-1PM) Course Structure
Physical Design Training 02/Nov (9AM-1PM) Course Structure
Functional Verification Training for Experienced engineers 26/Oct (9AM-1PM) Course Structure
Functional Verification Training for Freshers 26/Oct (9AM-1PM) Course Structure
SystemVerilog Training 26/Oct (9AM-1PM) Course Structure
Custom Layout Training 02/Nov (9AM-1PM) Course Structure

Courses in VLSI Front End domain

Course Course Details Start Date Course Duration Fees New Batch starts every
Functional Verification Training for Freshers VLSI Course Structure 26/Oct 20 Weeks 39000 5 weeks
Functional Verification Training for Experienced Engineers VLSI Course Structure 26/Oct 17 Weeks 32000 5 weeks
Systemverilog Training SV Course Structure 26/Oct 10 Weeks 19000 5 weeks
VLSI Internship VLSI Internship Structure 26/Oct 3 months/12 months 25000 or 39000 6 weeks
UVM Training UVM Course Structure 21/Sep 7 weeks 13000 8 weeks
Verilog Training Verilog Course Structure 26/Oct 5 Weeks 7500 5 weeks
VHDL Training VHDL Course Structure Adhoc 5 Weeks 7500 ad hoc

Courses in VLSI Backend

Course Course Details Start Date Course Duration Fee New Batch starts every
Physical Design Training Course Structure 02/Nov(9AM-1PM) 14 Weeks 37000 5 weeks
RedHawk (Power Integrity & IR Drop Analysis) Training Course Structure 21/Sep(9AM-1PM) 8 Weeks 16000 8 weeks
Synthesis and STA Training Course Structure 02/Nov(9AM-1PM) 12 Weeks 29000 5 weeks
DFT Training course structure 21/Sep(11AM-2:30PM) 12 Weeks 36000 5 weeks
Custom Layout & Physical Verification Training Course structure 02/Nov (8:30AM-1PM) 16 Weeks 36000 5 weeks

Courses in Embedded Systems

Course Course Details Start Date Course Duration Fees New Batch starts every
Embedded Systems Training Embedded Systems Course Structure 12/Oct(9AM-1PM) 15 Weeks 29000 8 weeks

SoC & Courses on Standard Protocols

Course Course Details Start Date Course Duration Fees New Batch starts every
ARM Training ARM Architecture Training Course Structure 05/Oct 6 Weeks 10000 Adhoc
DDR Protocol Training DDR Training Course Structure Adhoc 5 Weeks 6000 12 weeks
PCIe Protocol Training PCIe Training Course Structure 12/October 5 Weeks 8250 12 weeks
USB3.0 Protocol Training USB30 Course Structure Adhoc 5 Weeks 8250 12 weeks
SoC Design & Verification Training SoC Training Adhoc 6 Weeks 10000 10 weeks

Courses on Scripting Languages

Course Course Details Start Date Course Duration Fee New Batch starts every
PERL Training PERL Course Structure Adhoc 5 Weeks 4000 10 weeks
Python Training Python Course Structure 7/Sep 5 Weeks 4000 10 weeks
TCL Training TCL Course Structure Adhoc 4 Weeks 3000 10 weeks
SHELL Training SHELL Course Structure Adhoc 4 Weeks 3000 10 weeks

Call us for more details on VLSI Training course structure

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