Power consumption is significant aspect of increasingly complex SOCs, which are typically used for portable systems. Low power design techniques helps identify the power behavior and minimise the power consumption. Both portable and non-portable systems, requires efficient power management techniques.
This course introduces IEEE 1801 UPF for specifying the idle power management architecture.
Student will learn SoC power domain architecture , in UPF how to define power intent – supply_port, supply_net, power cells like power switches, isolation cells, level shifters , retention cells, power state table and gating logic. They will also learn how to update a design for the power intent, run the simulation to analyse the power behavior.
- Power Management – Need for low power
- CMOS basics w.r.t Power Consumption
- Low Power Techniques
- SoC and PMIC architectures
- UPF Concepts
- UPF design data flow
- UPF Power Intent commands
- Memory Controller architecture
- Memory Controller low power verification setup
- Running low power simulations
- How to debug low power issues
- Low power assertions and coverage
- Course is offered as both Classroom and Online course
- Next Batch: adhoc training (scheduled based on minimum number of students enrolling for the course)
- Duration: 3 Weeks, 4 Hours on Saturday & Sunday
- Fee : INR 4,500 +GST at 18%
- Certificate of course completion
- Send mail to firstname.lastname@example.org
- Phone: +91-9986194191
Who should take the course?
- DV engineers who wants to diversify their verification domain expertise.
- Understanding of SoC architectures, Verification of designs.
Is course completion certificate issued?
Yes. It is issued once student completes all the course assignments.
- UPF document
- Example codes for all UPF concepts.
- Design & Verification engineers looking for expertise in low power verification techniques.
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of bringing up low power verification environment for a complex SOC.