SPI, I2C and UART are the peripheral communication protocols targeted for low power, low complexity, low cost and low performance applications. These protocols are part of every SOC, including the complex mobile SOC and server SOC platforms. Hence learning protocols is an important aspect for every design and verification engineer.
SPI, I2C and UART protocol and UVC development is 5 weeks training focused on in-depth understanding of protocols and UVC development for these protocols.
SPI, I2C, UART Protocol
- Signals
- Timing diagrams
- Architecture
- Features
UVC Development for SPI, I2C and UART Protocols
- UVC architecture
- UVC components
- UVC types
- Master, Slave
- Active, Passive
- UVC test scenario listing down
- UVC component coding
- Driver, Sequencer, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
| Course | AMBA Protocol training, AXI VIP, AHB UVC and APB UVC Development | |
|---|---|---|
| Duration | 5 weeks | |
| Next Batch | Adhoc (Please call +91-9986194191 for more details) | |
| Demo Session | Adhoc | |
| Course Enrolment | Adhoc | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on course labs, interview preparation | ||
| Students also get support on complete project flow during weekdays as well. | ||
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) | |
| 8:30AM – 12:30PM (Theory session offered by trainer) | ||
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | ||
| Students will take the weekday tests and assignments from home. | ||
| New batch starts | Every 16 Weeks | |
| Fee | INR 6000 + GST@18% (Classroom training) | |
| Tool | Questasim & VCS | |
| Mode of training | Classroom training at Institute | |
| Online training using live training sessions | ||
| Tool Access | Access to tool at institute for 12 months | |
| Certificate | Issued based on 50% assignment completion as criteria | |
| Assignments | 3 | |
| Trainer | 14+ Years exp in RTL design & Functional verification |
What are the Course Prerequisites?
- Exposure to any bus protocols like I2C, SPI, etc
- Exposure to digital design concepts
Does course cover practical sessions on protocols?
Yes. Participant will gain exposure to following aspects
- VIP development for AXI3 protocol
- UVC development for AHB2 protocol
- UVC development for APB protocol
- Analysing AXI, AHB and APB timing diagrams in simulations
- Functional coverage analysis
- Assertion coding and debugging
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Course Material Shared
- AXI, AHB, APB protocol specifications
- VIP/UVC code for AXI, AHB, & APB protocols
- Short notes/checklist for each protocol
Target Audience:
- Verification engineers with no prior exposure to any protocols
- Verification engineers looking for better career opportunities, and looking to improve their profile
- Engineering college faculty looking to enhance their VLSI skill set
Trainer Profile
- Institute has multiple trainers handing front end domain courses. Average experience of trainers is 10+ years.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
