• All high speed protocols like USB3, PCIe, SATA, UFS, etc are all based on OSI architecture. Course focus on teaching all the required concepts of different layers in PCIe. Course also cover design & testbench implmentation for transaction, Data link and physical layers of PCIe.
    PCIe Technology Overview

  • PCIe Background
  • PCIe Architecture Overview
  • Configuration Overview
  • Address Space and Transaction Routing
    Transaction Layer:

  • TLP types and fields
  • Flow Control
  • Quality of Service
  • VC, TC and Transaction Ordering
    Data Link Layer:

  • DLLP types and fields
  • Flow control
  • Ack/Nak protocol
    Physical Layer:

  • Physical layer Logical for Gen1, Gen2, and Gen3
  • Physical layer Electrical for Gen1, Gen2, and Gen3
  • Link Initialization and Training
    Additional PCIe topics

  • Interrupt support
  • Error detection and handling
  • Power management
  • System Reset
Course PCIe Training
Duration 5 weeks
Next Batch 12/October
Demo Session 12/October(9AM – 12PM)
Registration 13/October
Schedule Both Saturday & Sunday(main session timings discussed during demo session)
Course repeats every 12 weeks
Fee INR 8250(all inclusive)
Mode of training Classroom training at VLSIGuru Institute(Horamavu)
Online training using live training sessions
Certificate Issued based on 50% assignment completion as criteria
Batch Size 20
Assignments 5
Trainer 13+ Years of industrial experience

What are the Course Prerequisites?

  • Exposure to standard bus protocols
  • Exposure to Testbench component coding using SystemVerilog

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be s

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts
  • PCIe specification & PCIe different layer design & testbench code.

Target Audience:

  • Verification engineers looking to learn advanced verification techniques
  • MTech & BTech freshers who are well versed with SV, and would like to learn advanced verification
  • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
  • Engineering college faculty looking to enhance their VLSI skill set

Trainer Profile

  • 12 years of work experience in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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