SoC Design & Verification

At least 60% of functional verification work in VLSI is based on SOC & Subsystem verification. It is essential for every verification engineer to gain expertise on SoC & Subsystem verification concepts. The course is for functional verification engineers with module level verification expertise and planning to explore SOC verification. This course is essential for every verification engineer with 5+ years of experience have never got exposure to SOC verification.

  1. SOC design & verification flow overview
  2. SOC Design concepts
  3. Processor boot concepts
  4. SOC Verification : Important aspects
  5. SOC Test bench architecture
  6. Setting up SOC TB environment
  7. SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
  8. SOC Test plan
  9. SOC Test case Flow
  10. SOC Test case Coding (C files & SV files)
  11. Running test cases & regression
  12. SOC Test debug
  13. Typical testcase issues
  14. Verification closure
  15. Performance requirements
  16. Gate level simulations
  17. Power Aware Simulations
    1. PAGLS
  18. EVCD generation
  19. Vector runs on VT setup
  20. Generating binaries for running on tester
  21. ECO
  22. RMA
  23. UVC in Testbench setup & sequence usage in SV testcase


  1. SOC FLOW:
    • SoC Architecture
    • Design Integration
      • Spy glass,
    • Functional Verification
    • Formal Verification (Connectivity Checks)
    • PA RTL simulations
    • GLS
    • PA GLS simulations (UPF)
    • Vector evcd generation
    • VT simulations on testers
    • Post silicon validation (VI)
  1. Design:
    • SoC Architecture
    • SoC Interconnects & NOCs
    • NoC Overview – Types of NOCs, purpose and diagram
    • SoC Digital & Analog Components
    • SoC Address Mapping
    • SoC Interrupt Mapping
    • SoC Frequency Plan
    • SoC Performance requirements
    • Features
    • DPLL
    • SoC Memories: Msg ram, Iram, DDR, Flash
    • SoC Subsystems
    • Low Power Verification
      • UPF
  1.  Important aspects:
    • SoC Architecture, understanding transaction matrix
    • Processor boot, SCF file,
    • interconnects
    • Memory preloading
    • DDR initialisation
    • PLL locking(LMN values)
    • TIC interface
    • Clock domains
    • Different clock mode
    • XO mode, at-speed mode
    • Interrupt handler
    • Processor interfaces: interfaces meant for fetching instruction, data code
    • I/O’s of SOC: Dedicated IO’s, and GPIOs
    • GPIO purpose : Pad muxing
    • CDC
    • Cycle slips
    • MMU, Physical address, virtual address
    • ARM instruction set basics
    • Types of verification : how they are different
    • Processor architectures
      • ARM, ARC, DSP
      • Cortex A series, M series
      • Impact on design architecture
    • Basics of ARM processors
      • Types of processors – Cortex-M series, A series.
      • ARM C, ASM compiler, linker.
      • Caches (L1 and L2).
      • Generic Interrupt controller.
      • Exceptions, Events – Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
      • Debug system – Basics of ARM debug sub system.
      • Scatter files.
      • How to set reset location to start booting.
      • Loading C code into memories – Front door, back door.
      • ARM Instruction example
  1. SOC Testbench Setup
    • SoC environment structure
    • SoC TB Architecture
    • Integrating UVC in to SoC TB
    • SoC Processor-TB interaction
  1.  Testplan:
    • register wr-rd, reset tests
    • Interrupt tests
    • targeting different frequency plans
    • Feature(use-case) tests
    • power aware tests
    • Fuse tests
    • End to end data transfer tests
    • Booting from different testcases
    • Address decoding access tests
    • Connectivity tests
  1. Testcase Flow:
    • TIC mode
    • Functional mode
    • Device Initialisation
    • DDR initialisation
    • Enabling DDR access to different processors
    • Processor boot sequence
    • Processor boot from different memories
    • C test Main function
      • Power uncollapse
      • Functional test
  1.  Coding testcases
    • Listing down test requirements, pass criteria
    • Power domains to be up
    • clock domains to be up, required frequencies
    • Understanding required flow to implement testcase
    • knowing library functions to implement above flow
    • understanding handshake between Native & SV code
  1. Setting up environment:
    • Design baseline
      • all design sub component latest baselines
    • verif baseline
      • all verif sub component latest baselines
    • Updating env for custom baseline
  1. Running testcases & regression:
    • Command line
    • sim_gui mode
    • Command line options
    • using force files, timing corners, frequency plans
  1. Debugging tests:
    • tarmac log
    • List file
    • mpf file
    • Simulation log
    • Wave dump debug
    • Message based debug
    • Warnings, errors
  1. Typical testcase issues:
    • Processor not booting
    • register looping
    • Not working at current frequency plan
    • pll not locked
    • Memory not preloaded
    • clocks not running
    • Access is not enabled to register or memory space
    • Simulation not proceeding in time
    • Simulation is proceeding in time but not completing (looping)
    • Interrupt not serviced
    • interrupt not generated
    • Signal not sampled
    • sub module functional issues
    • Denali errors
    • Memory loading ‘x’ debug
    • tied signals, unconnected ports
  1. Understanding chip stages
    • RTL code freeze
    • Base tapeout
    • Metal tapeout
    • ECO update
    • CS (customer shipment)
    • RMA
  1. Verification closure:
    • Regression 100% pass
    • 100% toggle coverage
    • reviews high level & low level
    • Performance requirements
    • Power requirements met
  1. Performance requirements
  2. Gate level simulations:
    • Significance
    • Choosing tests for GLS
  1. EVCD generation
    • Format
    • Need for EVCD
  1. Vector runs on VT setup
    • Production vectors
    • Characterisation vectors
  1. Generating binaries for running on tester
    • Vector debug
  1. ECO
    • What stage ECO is issued
  1. RMA
    • Significance
  1. Misc:
    • SoC Architecture:
    • SoC Interconnects
    • SoC Digital & Analog Components
    • SoC Address Mapping
    • SoC Interrupt Mapping
    • SoC Frequency Plan
    • SoC Performance requirements
    • Features
    • PLL
    • SoC Memories: Msg ram, Iram, DDR, Flash
  1. Processor booting from different memories
  2. UVC in Testbench setup & sequence usage in SV testcase

Currently there is no live sessions planned. You may enrol for e-learning course for self paced learning, with option to join upcoming batch with no additional cost.

Course SoC Design & Verification
Duration 7 weeks
Next Batch Adhoc (when course has a minimum strength)
Demo Session
Course repeats every 10 weeks
Fee INR 11000 +GST at 18%
Tool Questasim, Kiel
Mode of training Classroom training at VLSIGuru Institute, Banaswadi, ORR
Online training using live training sessions
Certificate Issued based on 50% assignment completion as criteria
Batch Size 20
Assignments 20
Trainer 12+ Years exp in RTL design & Functional verification

What are the Course Prerequisites?

  • Exposure to module level verification
  • Exposure to standard protocols like AXI, AHB, etc

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts
  • SoC architecture docs, protocol specification docs, etc.
  • Target Audience:
    • Verification engineers who have only exposure to Module level verificaiton, would like to widen verification exposure.
    • MTech & BTech freshers who are well versed with SV, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Multiple trainers, with experience of working on multiple SOC tape outs. All working in top-3 product companies.
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