RTL simulations is the basic requirement to signoff design cycle, but lately there is an increasing trend in the industry to run gate level simulations (GLS) before going into the last stage of chip manufacturing. Improvements in static verification tools like Static timing analysis (STA) and Equivalence Checking (EC) have leveraged GLS to some extent but so far none of the tools have been able to completely remove it. GLS still remains a significant step of the verification cycle footprint.
There is lot of motivation for running GLS even while STA is leveraging timing checks to major extent. GLS Training(VG-GLS) course will focus on teaching all the aspects of GLS from setup, test plan, frequency plans, SDF corners, and non-timing simulations. Course will also focus on various issues faced during GLS and debugging those. Course will involve hands on GLS project using complex gate level netlist.
- Need for GLS?
- GLS Concepts
- How GLS differs from STA
- GLS Testbench Setup
- GLS Testplan development
- GLS Frequency corners & timing modes, significance
- SDF detailed overview, SDF annotation
- GLS test debug & commonly faced issues
- Vector Simulations, evcd, debug
- GLS hands on project using a complex gate level netlist
- SOC GLS debug concepts
GLS Training(VG-GLS) Schedule
- Next Batch: 24/March/2019, 9AM
- Duration: 3 weeks
- Fee : INR 4,500 +GST at 18%
- Certificate of course completion
What are the Course Prerequisites?
- Expertise on digital design concepts
- Exposure to Testbench & testcase development using Verilog/SystemVerilog
What if I miss few sessions during course?
- Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- GLS session notes
- GLS interview questions
- Verification engineers looking to explore GLS & Vector simulations
- Engineering college faculty looking to enhance their VLSI skill set
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects