GLS Frequency corners & timing modes, significance
Understanding SDF contents
GLS : Good practices
Synchronizer flop forces
Command line options
Proper SDF mapping
No timing checks
Choosing right frequency
Debugging GLS failures
Log file debug
Adding optimal number of signals to waveform
Data flow and Schematic tracing
Common GLS issues
GLS advanced aspects
SOC GLS debug concepts
Two GLS hands on projects
Setting up test bench
Unit delay simulations
GLS regression and signoff
Gate level simulations is an important aspect of VLSI design flow. It helps validate the gate level netlist for setup and hold time violations and any reset or power up sequence issues.
There is lot of motivation for running GLS even while STA is leveraging timing checks to major extent. GLS course will focus on teaching all the aspects of GLS from setup, test plan, frequency plans, SDF corners, and non-timing simulations. Course will also focus on various issues faced during GLS and debugging those.
Course involves two hands on projects using complex gate level netlist.
Gate level simulations Training
Live training : 3 weeks eLearning : 25 hours
Saturday, Sunday, 9AM to 1PM
Mode of training
Live training for minimum of 10 participants or corporate training. eLearning with dedicated mentor for doubt clarifications.
Live training : INR 8K + GST eLearning : INR 7K + GST