Below is list of projects done as part of Verilog course. All these projects will be done in the live training sessions. All the codes will be done from scratch. There will be lab sessions where student will be doing the same with trainer guidance.
FIFO is a design component used for interfacing data transfer between two components either working on same frequency or a different frequencies. The design was implemented in such a way that there are no race or glitch conditions arise due to design working in two different clock domains. I have implemented both Synchronous FIFO and Asynchronous FIFO using Verilog and the RTL code also verified using Verilog.
SPI Controller is design block that acts as an interface between processor and SPI slaves. SPI architecture is based on one master and multiple slaves. SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers, address and data, other is SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, MISO and CS to connect master to slave. I was responsible for developing SPI Controller RTL code and verification of the same using Verilog.
- Listing down design features
- Setting up Testbench and testbench development
- Testcase coding
- Debug the testcases and analyse the waveforms
Interrupt controller is a design used to collect interrupts from various peripheral controllers and forwards the interrupts to processor on priority basis. This continues till all interrupts are serviced by processor. It interfaces with processor on one side using APB interface and another side with peripheral controller. Interrupt controller has configuration registers for programming the various peripheral priority levels, interrupt are processed based on these values. I was responsible for the complete functional verification flow starting from specification reading till verification closure. Testbench environment implemented using SV.
I2C Controller is a design block used for interfacing with I2C master with multiple I2C slaves. I2C controller has 2 interfaces, one is APB interface used for configuring the I2C registers, another is I2C interface using for connecting with I2C slaves. I2C uses SCL and SDA ports for interfacing master to slave. I was responsible for complete verification flow.
PISO(Parallel In Serial Out) and SIPO (Serial In Parallel Out) are required for Serialising and De-serialising data at PHY interface. These has two interfaces for data driving from parallel interface on one side to serial interface on another side and vice versa. It collects the serial incoming data and pushes in to shift register and drives it out to upper layers as a parallel data. It collects parallel incoming data from upper layers and drives it on serial interface. Design also includes buffer to achieve non-blocking data transfers in both transmit and receive paths.
- RTL Coding for both transmit and receive paths
- RTL integration
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
- RTL coding and verification of Dynamic pattern detector
- RTL coding and verification of Watchdog timer
- RTL coding and verification of memory wrapper
- RTL coding and verification of Dual port RAM
Below course material is shared as part of the course. All these are done as part of the regular sessions.
|Course material||Shared over google drive consists of IEEE Manual-Labs & project code|
|Course page access||Get login details from Admin|
|Assignments-Checklist-Session notes||Course page|
|Labs||Shared as part of course material and also shared every week|| |
|Gvim install & usage||Youtube video shared as part of course guidelines|
|How to use course material||Share as part of Course material|
|Resume update||Share as part of Course material|
|Session Notes||Uploaded to the course page|
|Interview Questions||Uploaded to course page|
|Labs for every week session||sent as mail attachment at the end of every week|
Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.