Custom layout training is 4.5 months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and io layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Majority of graduates lack good foundation in digital and analog design concepts, make them under prepared for industry requirements. Custom layout training will enable the candidate for job opportunities within 3 months from the start of course. Complete 4.5 months training ensures that the candidate is an expert in the domain.
Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law’s, Diode-operation, MOSFET’s, MOSEFT operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
Custom Layout Training
Custom layout training is 4.5 months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and io layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Majority of graduates lack good foundation in digital and analog design concepts, make them under prepared for industry requirements. Custom layout training will enable the candidate for job opportunities within 3 months from the start of course. Complete 4.5 months training ensures that the candidate is an expert in the domain.
Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law’s, Diode-operation, MOSFET’s, MOSEFT operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
ASIC Flow Overview
- Requirements
- Design specification & architecture
- RTL Coding
- RTL integration
- Functional verification
- Synthesis
- DFT
- Physical Design
- STA
- Custom Layout
- Physical Verification
- Post Silicon Validation
Advanced Digital Design
Essentials of UNIX/Linux
- Linux/UNIX OS, Shell
- Working with files, directories
- Commonly used commands
Semiconductor Basics
- Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor.
- Basic Passive and Active devices.
- Ohms law, Kirchoff laws
- Basic of circuit understanding
CMOS & FINFET Basics
- MOSFET Basics, Operations, few simple circuits & second order effects.
- MOSFET Detailed fabrication process.
- FinFET working, Fabrication, advantages & disadvantages.
Layout tool
- Layout Editor Tool
- Understanding the schematic symbols and parameters
- Creating and managing libraries and cell
- Commands for Layout editing.
- Commands for schematic editing.
- Verification : DRC and LVS
- Antenna effect, latchup, Electromigration, IR Drop
- Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
- Resistor, Capacitor layout techniques
- CMOS and BiCMOS layout techniques
- Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Advanced Layout Concepts
- Mismatches & Matching.
- Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects).
- Noises & Coupling.
- Different Types of process – Advantages & Disadvantages – Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet.
- Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines.
- Packaging.
Standard cell, IO, and Memory Layout
- Std Cell & Memories.
- IO Layout Guidelines : High speed IOs and High Speed Interfaces.
- Sense amplifier & Bit cell development
- Why memory layout different than analog layout
- Memory layout flow
- Types of memory layout (SRAM/DRAM/ROM)
- Introduction to SRAM memory layout
- Fixing few manually created leaf-cell errors which impact
- Abutment issues
- Impact of IR, EM and DFM .
- SRAM memory design architecture
- Words line and address line
- SRAM rows and column design
- Building blocks of SRAM
- Memory Bit cell
- Row decoder
- Word line driver
- Sense amplifier
- Control block
- Misc digital logic.
- Pitch Calculation for blocks.
- Power Planning
Analog and Mixed signal Layout
- High speed Analog Layout
- RF Layout guidelines with Transmission lines and inductor concepts
- Handling clocks
- Analog Circuits & Layout guidelines
- Single & Multi stage differential opamp layout
- current mirror layout
- PLL, DLL and Oscillators
- LDO and other regulators
- ADCs & DACs
- Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
- Large drivers
- input pair, differential routing, Power routing, offset minimising
- Power/Signal IR Drop
- cross-talk and coupling
- Electrostatic Discharge
- Deep Sub-micron Layout Issues
- Shallow Trench Isolation (LOD)
- Well Proximity Effect
Physical Verification concepts
- Design Rule Checks
- Layout Versus Schematic (LVS)
- Electrical Rule Checks (ERC)
- Antenna Checks
- Latch-up
- Reliability checks like EM and IR analysis
- Design for manufacturability (DFM)checks
- Electrostatic discharge (ESD) path checks
Assignments and hands on projects
- Assignments and multiple hands on projects
- Best Practices & Interview Questions.
Course is offered in both classroom and online training
| Custom Layout Training | |
|---|---|
| Duration | 18 weeks |
| Next Batches | 06/June |
| Demo Session | 06/June(9 AM – 1 PM) |
| Course commencement date | 07/June |
| Schedule | |
| Saturday & Sunday(9AM – 5PM) India time | |
| 9AM – 1PM (Theory session offered by trainer) | |
| 2PM – 5PM (Lab & tool based session guided by trainer). Students from US will get support in different time. | |
| Students will take the weekday tests and assignments from home. | |
| Students can also get support on complete project flow during weekdays in evenings. | |
| New batch starts | Every 7 Weeks |
| Fee | |
| INR 35,000 +GST at 18% (Classroom training) INR 44,000 +GST at 18%(Online training) | |
| Tools | Synopsys CDesigner, IC Validator |
| Mode of training | Classroom training at VLSIGuru Institute, ORR, Banaswadi |
| Online training using live gotomeeting sessions | |
| Tool Access | Tool access for 12 months at the institute |
| Certificate | Issued based on performance in evaluation tests |
| Batch Size | 30 |
| Assignments | 10 |
| Evaluation tests | 2 (one in the middle of the course, another towards end of the course) |
| Placement support | Institute does not give any commitment on job or number of opportunities, however student will be provided with opportunities till he/she gets job. |
| Trainer | 15+ Years of industrial experience |
What are the Course Prerequisites?
- Expertise on Digital & Analog design concepts
- Exposure to basic layout concepts
Course Material Shared:
- User Manual
- Layout Checklist
- Tool user guide
Target Audience:
- Graduates planning to make career as a custom layout design engineer
- Experienced engineers planning to change career domain
- Engineering college faculty looking to enhance their VLSI skill set
Trainer Profile
- 6+ years of rich experience of working in all aspects of custom layout from Analog, Memory, IO and Standard cell at various technology nodes
- Senior Director in a reputed Design company
