Custom and Analog Layout Training
Projects are the most significant part of any engineers(both fresher and experienced) resume. It is the projects that differentiate your resume from other resumes, which essentially helps your chances of getting through the interviews.
Below is the list of projects student will be doing as part of six months training. Student will be doing all these projects from scratch. These projects will provide student with expertise on par with a 2 to 3 years experienced engineer, in terms of all the skill set required. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
- Complete layout flow including
- Floor planning
- Schematic
- Layout
- Physical verification
1. Standard Cell Layout of Digital Gates
Description : Schematic, Layout design and verification for standard cell for NOT, NAND, NOR, AND, OR gate and Buffer.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
2. Level Shifter
Description : Designed the Layout for Level Shifter.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
3. Schmitt Trigger
Description : Designed the Layout for Schmitt Trigger.
Role : Layout Design and Layout Verification.
Challenges : Involved in placement, routing by taking care of minimum area and Verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
4. Single Stage OpAmp
Description : Single stage Op-Amp designed, one with NMOS differential pair and the other with PMOS differential pair whose input and output are Shielded. Common Centroid matching technique was used while implementing differential input pair. Taken care of Electro migration to manage current in the last stage which is a high gain stage and proper care was taken to avoid latch up.
Role : Layout Design for OpAmp and Layout verification.
Challenges : Involved in placement, matching of MOS devices, routing by taking care of Electro migration and Layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
5. 4-bit Flash ADC
Description : Designed layout for the 4-bit Flash Analog to Digital converter. Main Challenge was matching of the resistors as any variation in the Resistance would results in the improper output.
Role : Layout Design for Block and Top level.
Challenges : Floor-planning considering different devices and precise resistors Matching and their Internal routing constraints. Routing by taking Care of resistance, IR and Top-level layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
6. 4-bit DAC
Description : Designed the layout for 4 bit Digital to Analog converter. Main Challenge was the matching of the resistors.
Role : Layout Design for block level. Adjusted M1 and M2 pattern errors by adding fill cells and metal fills cleaned DRC, LVS by using the CPDS.
Challenges : Floor-planning considering resistor. Routing is one by taking care of IR, symmetry and top-level layout verification.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node : 28nm
7. Band Gap Reference with start-up circuit
Description : Designed the BGR with startup circuit. Main challenge was the matching of the resistors and symmetric routing.
Role : Layout Design for block level (BGR).
Challenges : Floor-planning considering different devices and BJTs and their internal routing constraints. Routing by taking care of Electro-migration, Latch-up and IR and top-level layout verification LVS/DRC.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node: 28nm
8. Low Drop-Out regulator circuit
Description : Designed the Layout for LDO using single stage Op-Amp as error amplifier with large PMOS and feedback resistors. In which matching, area, Electro migration and shielding constraints are taken into consideration. Proper care was taken about Electro migration to manage high current in the last stage which is a high current stage.
Role : Layout Design for block level and top level.
Challenges : Floor-planning considering different blocks and their internal routing constraints. Routing by taking care of electro migration, shielding symmetry, IR and top-level layout verification LVS/DRC.
Tools Used : Synopsys Custom Designer & IC Validator (for DRC/LVS).
Technology Node : 28nm
9. Phase Locked Loop
Technology Node : 28nm
Role : layout of VCO, Charge pump, phase detector Cleaned DRC, LVS of the above blocks
Challenges : Sharing of devices, area minimization and routing issues. Also, matching must be there in layout by proper techniques.
10. Serializer and Deserializer (SerDes)
Technology Node : 28nm
Role : Adjusted M1 and M2 pattern errors by adding fill cells and metal fills cleaned DRC, LVS.
Challenges : M1 layer is inbuilt present in Active devices, so M1 errors has to be cleaned without disturbing a floor plan. Also, need to clean the errors regarding higher metals
Custom layout training is 5.5 months course targeted for BTech, BE, MTech, ME, diploma graduates and experienced engineers planning to pursue career as a layout design engineer. Training will focus on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law’s, Diode-operation, MOSFET’s, MOSEFT operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
ASIC Flow Overview
- Requirements
- Design specification & architecture
- RTL Coding
- RTL integration
- Functional verification
- Synthesis
- DFT
- Physical Design
- STA
- Custom Layout
- Physical Verification
- Post Silicon Validation
Advanced Digital Design
www.vlsiguru.com/digital-design-complete
Essentials of UNIX/Linux
- Linux/UNIX OS, Shell
- Working with files, directories
- Commonly used commands
Semiconductor Basics
- Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor.
- Basic Passive and Active devices.
- Ohms law, Kirchoff laws
- Basic of circuit understanding
CMOS & FINFET Basics
- MOSFET Basics, Operations, few simple circuits & second order effects.
- MOSFET Detailed fabrication process.
- FinFET working, Fabrication, advantages & disadvantages.
Layout tool
- Layout Editor Tool
- Understanding the schematic symbols and parameters
- Creating and managing libraries and cell
- Commands for Layout editing.
- Commands for schematic editing.
- Verification : DRC and LVS
- Antenna effect, latchup, Electromigration, IR Drop
- Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
- Resistor, Capacitor layout techniques
- CMOS and BiCMOS layout techniques
- Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Advanced Layout Concepts
- Mismatches & Matching.
- Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects).
- Noises & Coupling.
- Different Types of process – Advantages & Disadvantages – Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet.
- Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines.
- Packaging.
Standard cell, IO, and Memory Layout
- Std Cell & Memories.
- IO Layout Guidelines : High speed IOs and High Speed Interfaces.
- Sense amplifier & Bit cell development
- Why memory layout different than analog layout
- Memory layout flow
- Types of memory layout (SRAM/DRAM/ROM)
- Introduction to SRAM memory layout
- Fixing few manually created leaf-cell errors which impact
- Abutment issues
- Impact of IR, EM and DFM .
- SRAM memory design architecture
- Words line and address line
- SRAM rows and column design
- Building blocks of SRAM
- Memory Bit cell
- Row decoder
- Word line driver
- Sense amplifier
- Control block
- Misc digital logic.
- Pitch Calculation for blocks.
- Power Planning
Analog and Mixed signal Layout
- High speed Analog Layout
- RF Layout guidelines with Transmission lines and inductor concepts
- Handling clocks
- Analog Circuits & Layout guidelines
- Single & Multi stage differential opamp layout
- current mirror layout
- PLL, DLL and Oscillators
- LDO and other regulators
- ADCs & DACs
- Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
- Large drivers
- input pair, differential routing, Power routing, offset minimising
- Power/Signal IR Drop
- cross-talk and coupling
- Electrostatic Discharge
- Deep Sub-micron Layout Issues
- Shallow Trench Isolation (LOD)
- Well Proximity Effect
Physical Verification concepts
- Design Rule Checks
- Layout Versus Schematic (LVS)
- Electrical Rule Checks (ERC)
- Antenna Checks
- Latch-up
- Reliability checks like EM and IR analysis
- Design for manufacturability (DFM)checks
- Electrostatic discharge (ESD) path checks
Assignments and hands on projects
- Assignments and multiple hands on projects
- Best Practices & Interview Questions.
Course is offered in both classroom and online training
| Custom Layout Training | |
|---|---|
| Duration | 5.5 months |
| Next Batch | 11/JUNE |
| Schedule | |
| Saturday & Sunday(9AM – 5PM) India time | |
| 9AM – 1PM (Theory session offered by trainer) | |
| 2PM – 5PM (Lab & tool based session guided by trainer). Students from US will get support in different time. | |
| Students can also get support on complete project flow during weekdays in evenings. | |
| New batch starts | Every 8 Weeks |
| Tools | Synopsys Custom Designer, IC Validator |
| Mode of training | Class room training and Live online training sessions |
| Tool Access | Tool access for complete course duration |
| Batch Size | 15 |
| Assignments | 10 |
What are the Course Prerequisites?
- Expertise on Digital & Analog design concepts
- Exposure to basic layout concepts
Course Material Shared:
- User Manual
- Layout Checklist
- Tool user guide
Target Audience:
- Graduates planning to make career as a custom layout design engineer
- Experienced engineers planning to change career domain
- Engineering college faculty looking to enhance their VLSI skill set
Trainer Profile
- 6+ years of rich experience of working in all aspects of custom layout from Analog, Memory, IO and Standard cell at various technology nodes
- Senior Director in a reputed Design company
-
- Fee: INR 45,000 + GST
- Confirm your course enrolment by making 5,000 INR transfer to below account.
- Payment schedule
- 5000 INR towards course enrolment
- 40000 + GST(overall)
- Half payment within 1 week of course commencement
- Remaining half within 1.5 month
