RTL Design and Integration Course is of 5 months duration focused on enabling participant with RTL integration job role. Training focus will be on RTL coding using Verilog & VHDL, manual integration, developing the glue logic during integration, tool based integration, linting, CDC, UPF, Synthesis and STA.
VLSI Front end domain(Pre-synthesis flow) jobs can be classified in to multiple categories as RTL coding, RTL integration, and Functional verification. VLSI design flow is completely driven by design IP reuse, hence majority of jobs in front end design will be based on RTL integration, which involves integrating multiple IP’s in to SOC as per architecture requirements. RTL integration engineer requires good exposure to RTL coding, Design constraints, Digital design concepts, good coding guidelines and exposure to Synthesis and STA concepts.
Like any other job role in VLSI design flow, RTL integration is also a tool intensive job. RTL Integration course will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA. Tools helps with quick turn around in time critical projects, where integration engineer is expected to release the design tag in short timelines. With growing design complexity and reducing timelines, it requires efficient techniques for RTL connectivity and developing the logic for various blocks integration. LINTING is a static analysis of the RTL code based on some set of rules and guidelines. When these rules or guidelines are broken, LINT tool flags errors or warnings, which need to be reviewed, fixed or waived by designer. This course discusses good amount of LINT rules and guidelines, which will enable audience to gain good design practices and perform LINTING if needed.
Course will also focus on Splyglass based CDC(Clock domain crossover) for the synchronisation of various signals moving across one clock domain to another. Course will focus on in-depth analysis of Lint and CDC checks with hands on integration project.
Similar to how we have multiple clocks in a System-On-Chip design we do have multiple power domains being used in modern SOCs for different reasons. Unified Power Format is IEEE standard developed by Accellera. This is used to ease the job of specifying, simulating and verifying the design with multiple power states and power islands. UPF is designed to specify power intent of a design at high level. UPF scripts mention the details of which power rails need to be connected to which IP, whether the register values need to be retained during power off, whether we need an isolation of design in case of power down and manages voltage levels shift as signals cross from one power domain to the other. In this course we discuss the need for multiple power domains, basics of UPF and some examples.
Clock Domain Crossing
Course | RTL Design and Integration Training |
---|---|
Duration | 5.5 months (Experienced engineers: 3.5 months without Verilog and Digital design training) |
Next Batch | 21/January |
Schedule | |
Freshers | Full week course |
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). | |
Weekdays sessions will be focused on training on Verilog labs, Digital Design, Linux and TCL scripting. | |
Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) |
8:30AM – 12:30PM (Theory session offered by trainer) | |
1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
Students will take the weekday tests and assignments from home. | |
Students also get support on complete project flow during weekdays as well. | |
New batch starts | Every 8 Weeks |
Tools | Synopsys Splyglass, Design compiler, Primetime, Core tools, Formality |
Mode of training | Classroom training at VLSIGuru Institute, ORR, Banaswadi |
Online training using live training sessions | |
Tool Access | Tool access for complete course duration |
Batch Size | 10 |
Assignments | 20 |
Course Material Shared:
Teacher is an important part of anybody's education.
I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.
I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.