Functional verification course for freshers (VG-FEDV) is a 6.5 months course structured to enable BTech/BE and MTech/ME freshers gain in depth exposure to all the aspects of VLSI Design and verification. VLSI design and verification course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, System Verilog, UVM, Linux, revision management and scripting. Course also includes training on soft skill for effective interview performance.
Lack of fundamentals in advanced digital design, Analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI design and verification course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. VLSI design and verification course is practical oriented with each aspect of course involving multiple hands on projects. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and PERL/Python scripting.
VLSI design and verification course includes VLSI Design flow(ASIC flow) training covering complete ASIC flow exposure from specifications till GDSII including Architecture, Specifications, RTL coding, lint checks, RTL integration, connectivity checks, functional verification, synthesis, Gate level simulations, formal equivalence checks, STA, placement and routing, clock tree synthesis, DFT, custom layout and post silicon validation. SOC Design and verification focus on SOC design concepts, SOC architecture, SOC verification concepts and differences when compared to module level verification.
Advanced Digital Design course focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronisers, timing violation fixing, etc.
Verilog and RTL coding course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.
Systemverilog course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.
RTL debug course will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
Linux OS course ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.
Scripting course will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry. Soft skill training will prepare student on how to face interviews effectively, right body language, etc.
VLSI design and verification course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.
Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
Teacher is an important part of anybody's education.
I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.
I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.