Functional verification course for freshers (VG-FEDV) is a 6 months course structured to enable BTech/BE and MTech/ME freshers gain in depth exposure to all the aspects of VLSI front end Design and verification. VLSI functional verification course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, Systemverilog, UVM, Linux, revision management and scripting. Course also includes training on soft skill for effective interview performance.
Lack of fundamentals in advanced digital design, analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI Front end training course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. Course is completely practical oriented with each aspect of course involving multiple hands on projects. All the courses are offered by trainers with 10+ years of relevant experience. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and scripting.
VLSI Design flow(ASIC flow) course covers complete ASIC flow exposure from specifications till GDSII including Architecture, Specifications, RTL coding, lint checks, RTL integration, connectivity checks, functional verification, synthesis, Gate level simulations, formal equivalence checks, STA, placement and routing, clock tree synthesis, DFT, custom layout and post silicon validation. SOC Design and verification focus on SOC design concepts, SOC architecture, SOC verification concepts and differences when compared to module level verification.
Advanced Digital Design course focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronisers, timing violation fixing, etc.
Verilog and RTL coding course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.
Systemverilog course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.
RTL debug course will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
Linux OS course ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.
Scripting course will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry.
Soft skill training will prepare student on how to face interviews effectively, right body language, etc.
Course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.
Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
This course is a super set of all other front end training courses, except for some advanced aspects of UVM not covered in this course. These advanced aspects are not required for a fresher.
- Covers all the topics covered in Verilog, Systemverilog courses
- Covers all the topics of UVM till AHB UVC coding.
- Training duration is split as below
- 7 weeks (Verilog, ASIC flow, Advanced Digital design)
- 12 weeks (Systemverilog, Linux OS, Python Scripting, Revision management)
- 5 weeks (UVM, SOC Design and verification overview, Softskills)
ASIC Flow
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
Advanced Digital Design concepts
- Digital Design basics
- combinational logic
- sequential logic, FF, latch, counters
- Memories
- Refer to Advanced digital design training page for detailed course contents
- www.vlsiguru.com/digital-design-complete
ASIC Verification Concepts
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
Verilog for Design and verification
- Verilog language constructs
- Verilog design coding examples covering more than 20 standard designs
- www.vlsiguru.com/verilog-training/
SystemVerilog for Advanced Verification
- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronization
- Processes, Threads, Tasks and Functions
- Randomization, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
Verification IP Development
- AXI Protocol Concepts : Features, Signals, Timing Diagrams
- AXI VIP Architecture Development
- VIP Component Coding
- AXI Slave model test case development
- Test Case debugging
RTL Debug
- Schematic tracing
- RTL tracing
- FIxing RTL and TB syntax and logical errors
Universal Memory Controller Functional verification
- Reading design specification
- Understanding design architecture, sub blocks, register definitions, interfaces
- Listing down features, scenarios
- Develop testplan
- Functional coverage point list down
- Develop Testbench architecture
- Testbench component coding and integration
- Skeletal TB structure coding
- Functional coding
- Develop sanity testcases(smoke testcases)
- Bringup testbench environment using sanity testcases
- Develop rest of testbench components
- Develop functional testcases
- Setup regression using Python script
- Verification closure
- Debug regression failures
- Functional, Code and assertion coverage analysis
UVM for functional verification
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM Testbench Architecture
- UVM Base classes
- UVM Macros
- UVM Messaging
- UVM simulation phases
- TLM 1.0
- Config db, Resource db, Factory
- Sequences, Sequence Library
- Virtual Sequences and virtual sequencers
- Developing scoreboard in UVM
- Developing testcases in UVM
- Command line processor
- UVC development for APB protocol
- UVC development for AHB protocol
- Developing configurable UVC’s
SOC Design and Verification concepts
- SOC Architecture overview
- SOC design concepts
- SOC verification concepts
- SOC Components
- SOC use cases
- SOC Testbench architecture
- SOC Test Case coding
- SOC verification differences with module verification
Linux
- Shells
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
- Makefiles
PERL/Python Scripting
- PERL Interpreter
- Variables
- File management
- Subroutines
- Regular expressions
- Object oriented PERL
- PERL modules
Soft Skill Training
- Facing interviews effectively
- industry work culture
- Group discussions
Course Assignments
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.
| Course | VLSI Front End Training for Freshers |
|---|---|
| Duration | 24 weeks |
| Next Batches | 26/Sept |
| Demo Session | 27/Sept (9AM – 1PM) |
| Course Enrolment | 27/Sept |
| Schedule | |
| Freshers | Full week course |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students. | |
| Weekdays sessions will be focused on course assignments, labs and interview focused sessions. | |
| Students also get support on complete project flow during weekdays as well. | |
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) |
| 8:30AM – 12:30PM (Theory session offered by trainer) | |
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
| Students will take the weekday tests and assignments from home. | |
| New batch starts | Every 8 Weeks |
| Fee | INR 39000 (Students based in India) INR 29000 (Fee for 21 weeks course including Verilog + SV + ASIC Flow + Digital Design+UVM Intro) |
| INR 44000+GST at 18% (Students based outside India) | |
| Tool | Questasim & VCS |
| Mode of training | Classroom training (currently not offered due to Covid) |
| Online training using live training sessions | |
| Tool Access | Access to tool at institute for 12 months |
| Certificate | Issued based on 50% assignment completion as criteria |
| Admission criteria | Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude |
| Assignments | 50 |
| Evaluation tests | 20 |
| Trainer | 12+ Years exp in RTL design & Functional verification |
| Content | Learning Schedule(T : Course Start Date) |
|---|---|
| Verilog for Design and Verification | T to T+8th week |
| VLSI Design Flow (ASIC flow) | T+1 week (Done during weekdays) |
| Advanced Digital Design | T+2 to T+3 week (Done during weekdays) |
| Systemverilog for functional verification | T+9 to T+21st week |
| Linux hands on training | T+14 to T+15th week(Done during weekdays) |
| PERL/Python Scripting | T+16 to T+18th week(Done during weekdays) |
| UVM for functional verification | T+22 to T+26th week |
| SOC concepts | T+24 week (Done during weekdays) |
| Soft skill Training | T+25th week (Done during weekdays) |
| Weekly learning schedule | |
|---|---|
| Day | Content (Students/working professionals missing weekday Digital/Linux/Scripting sessions will be provided with videos for missed sessions) |
| Saturday | 4 hours of training & 4 hours of labs(labs only for weekend students) |
| Sunday | 4 hours of training & 4 hours of labs(labs only for weekend students) |
| Monday | Labs for topics covered on Saturday and Sunday |
| Tuesday | Labs for topics covered on Saturday and Sunday |
| Wednesday | Labs for topics covered on Saturday and Sunday |
| Thursday | Labs for topics covered on Saturday and Sunday or Evaluation test |
| Friday | Break |
Below is the list of projects student will be doing as part of five months training. Institute provides guidance(trainer will be doing all these projects) on all these projects. If student gains expertise in these projects, learning will be on-par with a 2 to 3 years experienced engineer, in terms of all the skill set required. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB, SPI, I2C, UART, etc)
- Industry standard simulation tools like Questasim & VCS
- will gain debug expertise
- RTL coding and TB development
Project#1: Memory Controller Functional Verification using System Verilog
Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. As part of this design verification, we created testbench using SV to generate scenarios targeting all types of supported memories for different possible combinations & different sizes supported. We also developed monitor, reference model & checker as part self-checking testbench implementation.
Responsibilities
- Listing down design features
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
- Regression setup and debug
Project#2: Verification IP Development for AXI3.0 protocol using SV
AXI3.0 is an AMBA protocol used for high performance applications. AXI3.0 supports various features like out of order transactions, burst transfers, cacheble and bufferable transactions few among various features supported. VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
Responsibilities:
- Develop VIP Architecture to be compatible with both master and slave behavior
- List down AXI features and develop testplan for validating AHB VIP
- Develop AXI VIP components
- Integrated AXI Master VIP with slave VIP
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of VIP validation using coverage criteria
Project#3: UVC Development for AHB2.0 protocol using SV & UVM
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
Responsibilities:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
Project#4 : Ethernet Switch design verification using SV
Ethernet switch is a design with multiple ingress and multiple egress ports. Switch parses the packets coming on ingress port and routes them on corresponding egress port based on Destination address. I was responsible for setting up the complete TB environment including development of various TB components, reference model and checker.
Responsibilities:
- Develop TB Architecture to be compatible with configurable number of ingress and egress ports
- List down design features and develop testplan
- Develop and integrate TB components.
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of functional verification using coverage criteria.
Project#5 : Design & verification of Synchronous & Asynchronous FIFO using Verilog
Synchronous & Asynchronous FIFO are used to connect components transmitting and receiving data at different frequencies. I was responsible for developing the RTL and functional verification of the same using Verilog
Project#6 : Design & verification of SPI Controller using SV
SPI Controller is design block acts as an interface between SPI slaves and rest of the system. SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers, address and data, another is SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, MISO and CS to connect master to slave. I was responsible for developing SPI Controller RTL code and verification of the same using SV.
Responsibilities
- Listing down design features
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
Project#7 : Design & verification of Interrupt controller
Interrupt controller is a design used to collect interrupts from various peripheral controllers and forwards the interrupts to processor on priority basis. This continues till all interrupts are serviced by processor. It interfaces with processor on one side using APB interface and another side with peripheral controller from which it gets the interrupts. I was responsible for functional verification of the same using SV.
Project#8 : Design & verification of I2C controller
I2C Controller is a design block used for interfacing with multiple I2C slaves. I2C controller has 2 interfaces, one is APB interface used for configuring the I2C registers, another is I2C interface using for connecting with I2C slaves. I2C uses 2 ports for connecting master to slave.
Project#9 : Design & verification of PISO and SIPO using Verilog
PISO(Parallel In Serial Out) and SIPO (Serial In Parallel Out) are required for Serialising and De-serialising data at PHY interface. These has two interfaces for data driving from parallel interface on one side to serial interface on another side and vice versa. It collects the serial incoming data and pushes in to shift register and drives it out to upper layers as a parallel data. It collects parallel incoming data from upper layers and drives it on serial interface. Design also includes buffer to achieve non-blocking data transfers in both transmit and receive paths.
Responsibilities
- RTL Coding for both transmit and receive paths
- RTL integration
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
Why Course Fee is less compared to other institutes?
Institute is driven by philosophy of ‘Quality education at affordable fee’. Education should be affordable to majority of the people. Even otherwise basic courses like Digital Design, Verilog, SV, UVM, UNIX and Scripting all together can’t cost 1 lakh+. These are just languages and some projects.
Instead of asking us why charging less, please ask other institutes why charging so much for such basic skill set training? Let me tell you, tools are not costly as told by training institutes.
What are the Course Prerequisites?
- Expertise to C programming
- Exposure to Digital design basics
My college curriculum covers most of these topics, why should I opt for this course?
Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
Does course cover practical sessions on SystemVerilog usage?
- Each aspect of course is supported by lot of practical examples
- Ethernet switch project will be used as reference design for learning all SystemVerilog constructs
- All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Is it possible to cover so many things in 19 weeks?
- We have done it for 30 Batches so far, next batch is no exception
- Course requires student to spend at least 6+ hours of time a week to revise the concepts
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail your queries
- Option to meet trainer in person to clarify doubts
- Course Material Shared:
- Verilog course material, assignments, labs
- SV quick notes, IEEE manual
- SV Checklist
- SV Lab Examples
- AXI VIP Code
- Course Assignments
- Ethernet loopback design Testbench Code
- UNIX course material
- PERL Scripting course material
Students enrolled for the course(Log in to youtube using gmail Id to view below videos): Click here to view Course Page access video Click here to view Questasim usage video Click here to view VCS Usage video Click here to view GVIM editor video Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
- Multiple trainers with 10 years of average experience of working in Functional Verification domain across mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
- Experience of working on multiple complex module level projects
