Functional verification course for freshers is a 8 months course structured to enable students gain in depth exposure to all the aspects of VLSI design and functional verification. It is one of the exhaustive courses across the courses offered by the various institutes.
VLSI design and verification course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, System Verilog, UVM, Linux, version control and scripting. Course also includes training on soft skill for effective interview performance.
Lack of fundamentals in advanced digital design, Analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI design and verification course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. VLSI design and verification course is practical oriented with each aspect of course involving multiple hands on projects. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System Verilog, RTL debug, UNIX, and PERL/Python scripting.
Advanced Digital Design course focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronisers, timing violation fixing, etc.
Verilog and RTL coding course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.
Systemverilog course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.
RTL debug course will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
Linux OS course ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.
Scripting course will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry. Soft skill training will prepare student on how to face interviews effectively, right body language, etc.
VLSI design and verification course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.
Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 30+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc.
Please note, ‘VLSI Functional verification training’, ‘VLSI front end training for freshers’ and ‘VLSI design and verification training for freshers’ are all same courses and refer to the current course you are seeing.
Projects are the most significant part of any engineers(both fresher and experienced) resume. Every resume will by default have Verilog, SV and UVM. It is the projects that differentiate your resume from other resumes, which essentially helps your chances of getting through the interviews.
Below is the list of projects student will be doing as part of six months training. Student will be doing all these projects from scratch. These projects will provide student with expertise on par with a 2 to 3 years experienced engineer, in terms of all the skill set required. Student can work on additional projects to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
Course | VLSI Frontend Training for freshers |
---|---|
Duration | 28 weeks |
Next Batch | 09/December |
Schedule | |
Freshers | Full week course |
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students. | |
Weekdays sessions will be focused on course assignments, labs and interview focused sessions. | |
Students also get support on complete project flow during weekdays as well. | |
Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) |
8:30AM – 12:30PM (Theory session offered by trainer) | |
1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
Students will take the weekday tests and assignments from home. | |
New batch starts | Every 4 Weeks |
Tool | Questasim & VCS |
Mode of training | Classroom training & Online training |
Online training using live training sessions | |
Tool Access | Tool access for complete course duration |
Assignments | 50 |
Content | Learning Schedule(T : Course Start Date) |
---|---|
Verilog for Design and Verification | T to T+8th week |
VLSI Design Flow (ASIC flow) | T+1 week (Done during weekdays) |
Advanced Digital Design | T+1 to T+3 week (Done during weekdays) |
System Verilog for functional verification | T+9 to T+21st week |
Linux hands on training | T+14 to T+15th week(Done during weekdays) |
PERL/Python Scripting | T+16 to T+18th week(Done during weekdays) |
UVM for functional verification | T+22 to T+26th week |
SOC concepts | T+26 week (Done during weekdays) |
Soft skill Training | T+27th week (Done during weekdays) |
Senior Teacher
Teacher is an important part of anybody's education.
I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
I as a teacher, adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.
I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.