Course Overview

Functional verification course for freshers (VG-FEDV) is a 6.5 months course structured to enable BTech/BE and MTech/ME freshers gain in depth exposure to all the aspects of VLSI Design and verification. VLSI design and verification course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, System Verilog, UVM, Linux, revision management and scripting. Course also includes training on soft skill for effective interview performance.

Lack of fundamentals in advanced digital design, Analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI design and verification course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. VLSI design and verification course is practical oriented with each aspect of course involving multiple hands on projects. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and PERL/Python scripting.

VLSI design and verification course includes VLSI Design flow(ASIC flow) training covering complete ASIC flow exposure from specifications till GDSII including Architecture, Specifications, RTL coding, lint checks, RTL integration, connectivity checks, functional verification, synthesis, Gate level simulations, formal equivalence checks, STA, placement and routing, clock tree synthesis, DFT, custom layout and post silicon validation. SOC Design and verification focus on SOC design concepts, SOC architecture, SOC verification concepts and differences when compared to module level verification.

Advanced Digital Design course focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronisers, timing violation fixing, etc.

Verilog and RTL coding course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.

Systemverilog course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.

RTL debug course will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.

Linux OS course ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.

Scripting course will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry. Soft skill training will prepare student on how to face interviews effectively, right body language, etc.

VLSI design and verification course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.

Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.

This course is super set of all other front end training courses, except for some advanced aspects of UVM not covered in this course. These advanced aspects are not required for a fresher.

• Duration: 28 weeks (6.5 months)
• Covers all the topics covered in Verilog and System Verilog courses
• Covers all the topics of UVM till AHB UVC coding.
• 6.5 months split as below
  • 2 months (Verilog, ASIC flow, Advanced Digital design)
  • 3 months (Systemverilog, Linux OS, Python Scripting, Revision management)
  • 1.5 months (UVM, SOC Design and verification overview, Soft skills)

Please note, ‘VLSI Functional verification training’, ‘VLSI front end training for freshers’ and ‘VLSI design and verification training for freshers’ are all same courses and refer to the current course you are seeing.

Projects are the most significant part of any engineers(both fresher and experienced) resume. Every resume will by default have Verilog, SV and UVM. It is the projects that differentiate your resume from other resumes, which essentially helps your chances of getting through the interviews.

Below is the list of projects student will be doing as part of six months training. Student will be doing all these projects from scratch. These projects will provide student with expertise on par with a 2 to 3 years experienced engineer, in terms of all the skill set required. Student can work on additional projects to enhance resume for experienced job role.

By working on below projects, student will get familiar with:

• majority of standard protocols(AXI, AHB, APB, SPI, I2C, UART, etc)
• Industry standard simulation tools like Questasim & VCS
• Gain debug expertise
• RTL coding and TB development

• Course Material Shared:
  
  • Verilog course material, assignments, labs
  • SV quick notes, IEEE manual
  • SV Checklist
  • SV Lab Examples
  • AXI VIP Code
  • Course Assignments
  • Ethernet loopback design Testbench Code
  • UNIX course material
  • PERL Scripting course material

  Students enrolled for the course(Log in to youtube using gmail Id to view below videos):
  Click here to view Questasim usage video
  Click here to view VCS Usage video
  Click here to view GVIM editor video

  Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.

Srinivas Reddy

Senior Teacher

• Main trainer: Sreenivasa Reddy
  • Founder, VLSIGuru Institute
  • Dual Degree(VLSI Design), IIT Madras
  • 14 years of industry experience
  • 9 years professional training experience
    • Trained around 2000+ students
  • Lead Trainer for Mentor HEP 1.5 months program at Bangalore
  • Corporate trainer
• Supporting trainers:
  • 3 trainers currently working with Qualcomm, Intel and Samsung.
  • Experience of 10 years on average.