System Verilog for Functional Verification training (VG-SV) course is a 13 weeks course structured to enable engineers gain expertize in Systemverilog for functional verification including complex test bench development. System Verilog Training course is targeted towards engineers looking to explore advanced functional verification techniques involving constrained random verification, assertion based verification, and coverage based verification. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. System Verilog Training course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex test bench development coding, to ensure a smooth learning curve.
System Verilog Training course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AXI, APB), VIP development for these protocols and one industry standard project with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
System Verilog language in learnt using more than 200+ detailed examples covering all aspects of SV starting from data types, operators, OOPs(Classes), Arrays, Inter-process synchronisation, Interface, Program, constraints and randomisation, code coverage, functional coverage, DPI and assertions. These examples cover more than 90% of questions asked in VLSI interviews.
System Verilog Training course also covers multiple hands-on verification projects based on AXI, APB, Ethernet, and Memory controller. Learning starts from simple projects like Ethernet switch design verification to complex design verification projects involving Functional verification of Memory controller. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.
System Verilog Training course also involves 25+ detailed assignments (20+ assignments on SV language, 2 assignments on protocol, 2 on VIP development, 2 on industry standard projects). These assignments are prepared by industry experts covering all aspects of SV from language constructs, protocols and multiple industry standard projects. Student gets to work on these assignments with complete guidance from trainers and student learning is evaluated using completion of assignments as the sole criteria. Student is offered with multiple (more than 10+) interview opportunities based on performance in assignments.
Below is salient features of System Verilog Training in Functional Verification course.
Below is the list of projects student will be doing as part of five months training. Institute provides guidance(trainer will be doing all these projects) on all these projects. Student can work on additional projects, if he/she wants to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
Course | Systemverilog for Functional Verification |
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Duration | 14 weeks |
Next Batch | 21/January |
Schedule | |
Freshers | Full week course |
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | |
Weekdays sessions will be focused on training on Assignment solving sessions; evaluation tests; and labs. | |
Students also get support on complete project flow during weekdays as well. | |
Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) |
8:30AM – 12:30PM (Theory session offered by trainer) | |
1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
Students will take the weekday tests and assignments from home. | |
New batch starts | Every 8 Weeks |
Tool | Questasim & VCS |
Mode of training | Classroom training at VLSIGuru Institute(Horamavu) |
Online training using live sessions | |
Tool Access | Tool access for complete course duration |
Batch Size | 20 |
Assignments | 20 |
Content | Learning Schedule(T : Course Start Date) |
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Systemverilog language constructs | T to T+7th week |
AXI Protocol and AXI VIP Development | T+8 to T+10th week |
Industry standard project with detailed functional verification flow(Spec to coverage) | T+11 to T+14th week |
Systemverilog Material | Access |
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Course material | Shared over google drive consists of IEEE Manual-Labs & project code |
Course page access | Get login details from Admin |
Assignments-Checklist-Session notes | Course page |
Labs | Shared as part of course material and also shared every week |
Gvim install & usage | Youtube video shared as part of course guidelines |
How to use course material | Shared as part of Course material |
Resume update | Course page |
Interview Questions | Uploaded to course page |
Labs for every week session | sent as mail attachment at the end of every week |
Students enrolled for the course(Log in to youtube using gmail Id to view below videos): |
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Click here to view Course Page access video |
Click here to view Questasim usage video |
Click here to view VCS Usage video |
Click here to view GVIM editor video |
Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
Systemverilog course checklist:
• Added to whatsapp group
• Course material shared
• User login created (mail id is the password, change password after logging in)
• How to use Questasim, GVIM
• Session labs received at the end of every week
• Session notes
• Assignments
• Evaluation tests
Teacher is an important part of anybody's education.
I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.
I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.