System Verilog for Functional Verification training (VG-SV) course is a 13 weeks course structured to enable engineers gain expertize in Systemverilog for functional verification including complex test bench development. System Verilog Training course is targeted towards engineers looking to explore advanced functional verification techniques involving constrained random verification, assertion based verification, and coverage based verification. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. System Verilog Training course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex test bench development coding, to ensure a smooth learning curve.
System Verilog Training course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AXI, APB), VIP development for these protocols and one industry standard project with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
System Verilog language in learnt using more than 200+ detailed examples covering all aspects of SV starting from data types, operators, OOPs(Classes), Arrays, Inter-process synchronisation, Interface, Program, constraints and randomisation, code coverage, functional coverage, DPI and assertions. These examples cover more than 90% of questions asked in VLSI interviews.
System Verilog Training course also covers multiple hands-on verification projects based on AXI, APB, Ethernet, and Memory controller. Learning starts from simple projects like Ethernet switch design verification to complex design verification projects involving Functional verification of Memory controller. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.
System Verilog Training course also involves 25+ detailed assignments (20+ assignments on SV language, 2 assignments on protocol, 2 on VIP development, 2 on industry standard projects). These assignments are prepared by industry experts covering all aspects of SV from language constructs, protocols and multiple industry standard projects. Student gets to work on these assignments with complete guidance from trainers and student learning is evaluated using completion of assignments as the sole criteria. Student is offered with multiple (more than 10+) interview opportunities based on performance in assignments.
Below is salient features of System Verilog Training in Functional Verification course.
- SV Language construct learning using 200+ detailed examples
- AXI Protocol & AXI VIP Development
- APB protocol, APB VIP Development
- Memory Controller Functional Verification
- 20+ detailed assignments covering all aspects of SV, AXI, APB, and Memory controller project.
SystemVerilog language constructs
- Design and verification building blocks
- Design elements
- Modules
- Programs
- Interfaces
- Checkers
- Primitives
- Subroutines
- Packages
- Configurations
- Overview of hierarchy
- Compilation and elaboration
- Name spaces
- Simulation time units and precision
- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronisation
- Processes, Threads, Tasks and Functions
- Randomisation, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
ASIC Verification Concepts
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
AXI4.0 protocol and AXI Verification IP Development
- AXI4.0 Protocol : Features, Signals, Timing Diagrams
- AXI VIP Architecture
- VIP Component Coding
- AXI Slave model testcase coding
- Testcase debugging
Complex Module Verification from specification to verification closure
- Specification analysis
- Verification Plan creation
- Feature & Scenario Listing down
- TB architecture creation
- Building Top level verification environment
- TB component coding and integration
- Sanity test case and environment bring up
- Complete test case coding
- Building regression test suite
- Functional coverage and code coverage analysis
Course Assignments
- VIP Development for one of OCP/Wishbone/APB/Ethernet Protocols
- Verification of PCIEx Physical Layer LTSSM FSM from scratch
- Functional Verification of a complex module
Below is the list of projects student will be doing as part of five months training. Institute provides guidance(trainer will be doing all these projects) on all these projects. Student can work on additional projects, if he/she wants to enhance resume for experienced job role.
By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB etc)
- Industry standard simulation tools like Questasim & VCS
- Debug expertise
- TB development
Project#1: Memory Controller Functional Verification using System Verilog
DMA Controller is Dual core design used to replace two CPU functions, memory copy and peripheral control. The Dual core design ensures that, one core can be dedicated used for memory copy requests and other for slow peripheral devices. The different cores can be configured to completely different topographies, saving area, power and improving performance. Design is implemented with 64 bit AXI bus. Design has multiple interrupts to interface with multiple processors. Design supports various features like Block transfer, Scheduled channels, Joint mode, Independent mode, Outstanding mode and three level priority modes.
I have worked on all the aspects of Design verification starting from reading the specification till regression setup and coverage analysis for verification closure. This project will help student gain expertise in coverage analysis, testcase development, test debug and understanding minute aspects of design code and specification.
Responsibilities
- Listing down design features
- Functional coverage point listing down
- Setting up Testbench and testbench component coding.
- Testplan development
- Register model development and integration
- Testcase coding
- Reference model and checker coding
- Regression setup and debug
- Functional and code coverage analysis
Project#2: Verification IP Development for AXI3.0 protocol using SV
AXI3.0 is an AMBA protocol used for high performance applications. I was part of team which developed VIP for this protocol. VIP developed targeting both master and slave. Developed all the VIP components and scenarios for various AXI features.
Project#3: Ethernet Switch design verification using SV
Ethernet switch is a design with multiple ingress and multiple egress ports. Switch parses the packets coming on ingress port and routes them on corresponding egress port based on Destination address. I was responsible for setting up the complete TB environment including development of various TB components, reference model and checker.
| Course | Systemverilog for Functional Verification |
|---|---|
| Duration | 14 weeks |
| Next Batch | 22/JANUARY |
| Schedule | |
| Freshers | Full week course |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | |
| Weekdays sessions will be focused on training on Assignment solving sessions; evaluation tests; and labs. | |
| Students also get support on complete project flow during weekdays as well. | |
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) |
| 8:30AM – 12:30PM (Theory session offered by trainer) | |
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | |
| Students will take the weekday tests and assignments from home. | |
| New batch starts | Every 8 Weeks |
| Tool | Questasim & VCS |
| Mode of training | Classroom training at VLSIGuru Institute(Horamavu) |
| Online training using live sessions | |
| Tool Access | Tool access for complete course duration |
| Batch Size | 20 |
| Assignments | 20 |
| Content | Learning Schedule(T : Course Start Date) |
|---|---|
| Systemverilog language constructs | T to T+7th week |
| AXI Protocol and AXI VIP Development | T+8 to T+10th week |
| Industry standard project with detailed functional verification flow(Spec to coverage) | T+11 to T+14th week |
Why fee is charged less compared to other institutes?
- Institute philosophy : ‘Quality education at affordable fee’. All courses are structured to make them affordable for everyone to undergo training.
- Low cost does not mean low quality course; our SV training course is amongst the best SV training course available.
What are the Course Prerequisites?
- Verilog & Digital Design
- Exposure to coding design & testbench using Verilog (Ex: FIFO design & verification using Verilog)
Does course cover practical sessions on SystemVerilog usage?
- Each aspect of course is supported by lot of practical examples
- Ethernet switch design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
- All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student gets complete hands on exposure
Is it possible to cover so many things in 10 weeks?
- It is possible to cover whole SV training content including projects in 10 weeks(extended by 1 week if required). This will also require student also to spend dedicated time every week to revise the course topics and complete assignments as per schedule.
- 50 batches of SV training is completed so far since we started in 2012.
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, you will get the support even after course completion
| Systemverilog Material | Access |
|---|---|
| Course material | Shared over google drive consists of IEEE Manual-Labs & project code |
| Course page access | Get login details from Admin |
| Assignments-Checklist-Session notes | Course page |
| Labs | Shared as part of course material and also shared every week |
| Gvim install & usage | Youtube video shared as part of course guidelines |
| How to use course material | Shared as part of Course material |
| Resume update | Course page |
| Interview Questions | Uploaded to course page |
| Labs for every week session | sent as mail attachment at the end of every week |
| Students enrolled for the course(Log in to youtube using gmail Id to view below videos): |
|---|
| Click here to view Course Page access video |
| Click here to view Questasim usage video |
| Click here to view VCS Usage video |
| Click here to view GVIM editor video |
Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
Systemverilog course checklist:
• Added to whatsapp group
• Course material shared
• User login created (mail id is the password, change password after logging in)
• How to use Questasim, GVIM
• Session labs received at the end of every week
• Session notes
• Assignments
• Evaluation tests
- 13+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
- Fee: INR 23000 + GST
- Confirm your course enrolment by making 5,000 INR transfer to below account.
- Remaining fee can be paid in 2 instalments with gap of 1.5 months
