Course Overview
Syllabus
Projects
Schedule
FAQs
Course Material
Certificate
Trainer
Demo
Course Overview
Course Overview
VLSI Front end course for Experienced Engineers (VG-FEDV) course is a 19 weeks course structured to enable experienced engineers gain expertise in functional verification. Majority cases, engineers does not get the hands on exposure to SV & UVM based testbench development, most of times goes in testcase coding and debug, leaving with very minimal SV & UVM expertise. This course is targeted for such engineers, to enable them get hands on exposure to complete Testbench development using SV & UVM.
Course includes more than 40+ assignments covering various aspects of Systemverilog, AXI Protocol, AXI VIP Development, Memory Controller verification, UVM constructs, AHB Protocol, AHB UVC Development and AHB Interconnect functional verification. All the aspects of the course are covered using practical examples. Systemverilog course involves more than 250+ examples covering all the aspects of Systemverilog. UVM training involves more than 100+ examples. All the examples and projects are developed from scratch as part of course sessions.
Syllabus
Course content is same as Systemverilog course and UVM course
- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronization
- Processes, Threads, Tasks and Functions
- Randomization, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
- AXI Protocol Concepts : Features, Signals, Timing Diagrams
- AXI VIP Architecture Development
- VIP Component Coding
- AXI Slave model test case development
- Test Case debugging
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
- Reading Specification
- Feature listing down
- Scenario Listing down
- Functional coverage listing down
- Coverage Implementation
- Testplan creation
- Testbench architecture development
- Testbench component coding
- Testcase coding and debug
- Assertions coding
- Regression setup
- Regression debug
- Verification closure
- Regression closure
- Functional & Code coverage closure
- AHB Interconnect verification project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- What is UVM? Need for a methodology?
- How UVM evolved?
- OVM, AVM, RVM, NVM, eRM
- UVM class library
- Classification of base classes in various categories
- OOP basics
- Encapsulation
- Inheritance
- Polymorphism
- Parameterized classes
- Parameterized macros
- Static properties and static methods
- Abstract classes
- Pure virtual methods
- How above aspect correlates with UVM implementation.
- UVM Class Library, Macros, Utilities
- Detailed overview of important UVM base classes, Macros and Utility classes.
- UVM TB Architecture
- Setting up a UVM based testbench for APB protocol from scratch.
- Significance of uvm_root in UVM based testbenches.
- run_test, how it starts whole TB flow.
- Command line processor
- Reporting classes
- Uvm_report_object
- Uvm_report_handler
- Uvm_report_server
- Detailed examples on use of methods in these classes.
- Objections
- UVM Factory
- Configuration DB, Resource DB
- Detailed usage of both data bases.
- How config_db is related to resource_db?
- Using config_db to change the testbench architecture.
- TLM1.0
- Push
- Pull
- FIFO
- Analysis
- Complex example on AHB to AXI transaction conversion.
- Simulation Phases
- UVM common phases
- Scheduled phases
- Sequences, Sequencers
- Default sequence
- p_sequencer
- m_sequencer
- Test case development
- Different styles of mapping testcase to sequence
- Using default sequence and scheduled phases
- Using sequence start method
- Different styles of mapping testcase to sequence
- Configuring TB Environment
- Advanced aspects of developing a highly configurable test bench environment.
- Concept of knobs of test case scenario generation
- Using top level parameters to control the overall TB architecture
- AHB Protocol and AHB UVC development
- Coding from scratch with detailed explanation of each aspect.
- Setting up a highly configurable UVC to meet different TB requirements.
- Different testbench component coding
- Monitor
- Coverage
- Scoreboard
- Checkers
- Assertions
- Different styles of sequence development
- `uvm_do
- Start_item and finish_item
- Using existing sequences
- Sequence library
- Creating complex test cases using sequence library
- Virtual Sequencer, Virtual sequences
- Different types of sequences used in test benches
- Reset sequence
- Power up sequence
- interrupt handling sequence
- DMA handling sequence
- FSM verification sequence
- Layered sequence development
- How to create multiple layers of sequences
- Creating complex test cases using layered sequences
- Virtual sequence library
- Creating test cases using virtual sequence library
- Synchronization classes
- uvm_barrier
- uvm_event
- Container classes
- Policy classes
- uvm_printer
- uvm_recorder
- uvm_packer
- uvm_comparer
- Comparators
- In order comparator
- Algorithmic comparator
- TLM2.0
- Blocking transport
- Non-blocking transport
- Register Layer development for USB2.0 core
- Note: Doesn’t involve USB2.0 core verification
- Connecting multiple UVCs
- How to setup a complex testbench environment with multiple UVC’s connected.
- uvm_heartbeat
- How to check test bench status using heartbeat
- uvm_report_catcher
- How to handle error testcases using report catcher
- Phase jumping
- uvm_domain
- Reading Specification
- Feature listing down
- Scenario Listing down
- Functional coverage listing down
- Coverage Implementation
- Testplan creation
- Testbench architecture development
- Testbench component coding
- Testcase coding and debug
- Assertions coding
- Regression setup
- Regression debug
- Verification closure
- Regression closure
- Functional & Code coverage closure
40+ detailed assignments covering all aspects of SV & UVM.
Projects
Below is the list of projects student will be doing as part of 19 weeks training. Institute provides guidance(trainer will be doing all these projects) on all these projects. If student gains expertise in these projects, learning will be on-par with a 2 to 3 years experienced engineer, in terms of skill set required. Student can work on additional projects, if he/she wants to enhance resume for experienced job role.By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB, SDRAM, Ethernet, etc)
- Industry standard simulation tools like Questasim & VCS
- RTL debug expertise
- RTL coding and TB development
DMA Controller is Dual core design used to replace two CPU functions, memory copy and peripheral control. The Dual core design ensures that, one core can be dedicated used for memory copy requests and other for slow peripheral devices. The different cores can be configured to completely different topographies, saving area, power and improving performance. Design is implemented with 64 bit AXI bus. Design has multiple interrupts to interface with multiple processors. Design supports various features like Block transfer, Scheduled channels, Joint mode, Independent mode, Outstanding mode and three level priority modes.
I have worked on all the aspects of Design verification starting from reading the specification till regression setup and coverage analysis for verification closure. This project will help student gain expertise in coverage analysis, testcase development, test debug and understanding minute aspects of design code and specification.
Responsibilities
- Listing down design features
- Functional coverage point listing down
- Setting up Testbench and testbench component coding.
- Testplan development
- Register model development and integration
- Testcase coding
- Reference model and checker coding
- Regression setup and debug
- Functional and code coverage analysis
AXI3.0 is an AMBA protocol used for high performance applications. AXI3.0 supports various features like out of order transactions, burst transfers, cacheble and bufferable transactions few among various features supported. VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
Responsibilities:
- Develop VIP Architecture to be compatible with both master and slave behavior
- List down AXI features and develop testplan for validating AHB VIP
- Develop AXI VIP components
- Integrated AXI Master VIP with slave VIP
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of VIP validation using coverage criteria
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
Responsibilities:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
Ethernet switch is a design with multiple ingress and multiple egress ports. Switch parses the packets coming on ingress port and routes them on corresponding egress port based on Destination address. I was responsible for setting up the complete TB environment including development of various TB components, reference model and checker.
AHB Interconnect is a design with configurable number of masters and slave interface. Design routes the AHB transactions at master interfaces to corresponding slaves. I was responsible for setting up configurable TB using SV & UVM for interconnect verification. I have also developed testcases and sequences for verifying various design features.
USB2.0 core is a design used for interface UTMI interface of USB Host with USB function controller. USB2.0 core has three interfaces, one for UTMI interfacing, second for functional controller interfacing and third for buffer memory. USB2.0 design has 69 registers for configuration USB core behaviour including Endpoints. I was responsible for developing register model for USB2.0 core using SV & UVM.
Schedule
| Course | VLSI frontend course for experienced engineers |
|---|---|
| Duration | 22 weeks |
| Next Batch | 1/April |
| Schedule | Saturday & Sunday(8:30AM – 4:00PM India time) |
| 8:30AM – 12PM (Trainer led theory and lab sessions) | |
| 1PM to 4PM (Mentor guided lab & assignment solving sessions) | |
| New batch starts | every 8 weeks |
| Tool | Questasim & VCS |
| Mode of training | Classroom training & Online Training |
| Online training using live training sessions | |
| Tool Access | Tool access for complete course duration |
| Assignments | 40 |
FAQs
- Expertise on Verilog programming
- Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
- Each aspect of course is supported by lot of practical examples
- Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
- All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- We have done it for 35 Batches so far, next batch is no exception
- Course requires student to spend at least 6+ hours of time a week to revise the concepts
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail your queries
- Option to meet trainer in person to clarify doubts
Course Material
Course Material Shared:
- Verilog course material, assignments, labs
- SV quick notes, IEEE manual
- SV Checklist
- SV Lab Examples
- AXI VIP Code
- Course Assignments
- Ethernet loopback design Testbench Code
- UNIX course material
- PERL Scripting course material
Certificate
Trainer
Experienced Trainer
- Main trainer: Sreenivasa Reddy
- Founder, VLSIGuru Institute
- Dual Degree(VLSI Design), IIT Madras
- 14 years of industry experience
- 9 years professional training experience
- Trained around 2000+ students
- Lead Trainer for Mentor HEP 1.5 months program at Bangalore
- Corporate trainer
- Supporting trainers:
- 3 trainers currently working with Qualcomm, Intel and Samsung.
- Experience of 10 years on average.
Demo
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation