Syllabus
Course Overview
Schedule
Demo
FAQs
Trainer
Audience
certificate
Syllabus
Introduction to on-chip protocols
- Protocol overview
- AXI revisions
- AXI based system architecture
- Global signals
- Write address channel signals
- Write data channel signals
- Write response channel signals
- Read address channel signals
- Read data channel signals
- Low power interface signals
- Basic write and read transactions
- Relationship between channels
- Transaction structure
- Transaction types and attributes
- AXI3 memory attribute signalling
- AXI4 changes to memory attribute signalling
- Memory types
- Mismatched memory attributes
- Transaction buffering
- Access permissions
- AXI transaction identifiers
- Transaction ID
- Transaction ordering
- Definition of ordering model
- Master ordering
- Interconnect ordering
- Slave ordering
- Response before final destination
- Single-copy atomicity size
- Exclusive accesses
- Locked accesses
- Atomic access signaling
- QoS signaling
- Multiple region signaling
- User-defined signaling
- Low power interface signals
- Low power clock control
- Interoperability principles
- Major Interface categories
- Default signal values
- VIP architecture
- VIP components
- VIP types
- Master, Slave
- Active, Passive
- VIP test scenario listing down
- VIP component coding
- Driver, Generator, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
Enhance AXI3 VIP for AXI4 additional features
- QoS signaling
- Multiple region signaling
- User-defined signaling
- Low power interface
Introduction
- About the protocol
- AHB revisions
- Operation
- Global signals
- Master signals
- Slave signals
- Decoder signals
- Multiplexor signals
- Basic transfers
- Transfer types
- Locked transfers
- Transfer size
- Burst operation
- Waited transfers
- Protection control
- Memory types
- Secure transfers
- Interconnect Address decoding Read data and response multiplexor
- Slave transfer responses
- Data buses
- Endianness
- Data bus width
- Clock and reset requirements
- Introduction
- Exclusive Access Monitor
- Exclusive access signaling
- Exclusive Transfer restrictions
- Single-copy atomicity size
- Multi-copy atomicity
- User signal description
- User signal interconnect recommendations
- UVC architecture
- UVC components
- UVC types
- Master, Slave
- Active, Passive
- UVC test scenario listing down
- UVC component coding
- Driver, Sequencer, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
- APB protocol introduction
- Signal descriptions
- Transfers
- Operating states
- Develop APB UVC for master and slave
- APB master UVC validation using slave UVC
Course Overview
Course Overview
AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.
AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.
Schedule
| Course | AMBA Protocol training, AXI VIP, AHB UVC and APB UVC Development |
|---|---|
| Duration | Live training : 6 weeks eLearning : 45 hours |
| Course Start date | |
| Schedule | |
| Freshers | 6 days/week 4 hours/day, 9:30AM to 1:30PM |
| Working professionals | Saturday & Sunday 9:30AM – 1:30PM India time Access to all the session recorded videos for entire course duration. |
| New batch starts | Every 10 Weeks |
| Fee | Live training : INR 11,000 + GST eLearning : INR 9,500 + GST |
| Tool | Questasim & VCS |
| Mode of training | Live training for minimum of 10 participants or corporate training. eLearning with dedicated mentor for doubt clarifications. |
| Tool Access | 24×7 access to tool for entire course duration |
| Assignments | 5 |
Demo
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to any bus protocols like I2C, SPI, etc
- Exposure to digital design concepts
Yes. Participant will gain exposure to following aspects
- VIP development for AXI3 protocol
- UVC development for AHB2 protocol
- UVC development for APB protocol
- Analysing AXI, AHB and APB timing diagrams in simulations
- Functional coverage analysis
- Assertion coding and debugging
Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- Institute has multiple trainers handing front end domain courses. Average experience of trainers is 10+ years.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Audience
Target Audience:
- Verification engineers with no prior exposure to any AMBA protocol.
- Verification engineers looking for better career opportunities, and looking to improve their profiel
- Engineering college faculty looking to enhance their VLSI skill set
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- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- mock interview
- Industry Standard Projects
- Support with resume update