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STA Training is designed to make the Engineer or Designer understand the complete Timing SignOff strategies for successful and confident Tape-Out of the Design to the Semiconductor Fabrication House. Since timing is the heart beat of any chip, thorough understanding of timing concepts, development of Timing constraints are given through this STA Training especially when it comes to Ultra Deep Sub-Micron Technologies such as 28nm, 20nm, 14nm, 10nm. There are multiple parameters that decide how the timing of a chip would be functioning like Transition times of Clock phases and Data Path signals, Process and Voltage and Temperature (PVT) variations, Crosstalk noise affecting functionality of the chip, Crosstalk Delay affecting timing of the chip, which will be covered in greater detail in this STA Training. Other topics such as Advanced OCV, requirement of Clock path tweaking to meet desired frequency of the Chip will be discussed extensively in this STA Training. Pessimism inclusion when design is taped-out has been a norm to avoid any Silicon surprises but for higher frequency Designs on lower technology nodes, pessimism beyond a limit could be an over-do in which case pessimism-Removal is done through Path-Based Analysis rather than Graph based Analysis. This topic is covered with fine clarity in this STA Training. Above all, the fundamental part of setup and hold time fixing covering the above points are the key aspects of this STA Training. Tools used are Cadence Analysis Tool (Encounter Timing System or Tempus) for this STA training. Candidates will get access to tool both at institute and has option to connect to servers from home using Secure VPN to work on two SignOff projects hands on.Fixing of timing violations based on Sign-Off analysis for Multi Mode Multi Corner though ECOs would be across the breadth of this STA Training. Objective of this STA training is to shape graduating Bachelor’s and Master’s degree studentsas well as Physical Design Engineers explore opportunities in Block Level as well as Full Chip STA.

Below are the STA Training topics ((Also include this in sylubus))

SignOff STA Training topics :

  • Fundamental Setup and Hold Timing Checks
  • Timing Arcs across Design Instances
  • Stage Delay covering Cell Delay and Net Delay
  • Asynchronous Flop, recovery and removal checks
  • Cross Clock Timing Analysis
  • Interface Timing Analysis (between reg and IO)
  • Clock group based timing analysis
  • Crosstalk Delay and Crosstalk Noise
  • Advanced On Chip Variation, CPPR
  • Multi-Mode Multi-Corner timing analysis
  • Graph Based and Path based analysis
  • Timing DRC – Transition, Capacitance, Fanout fixes.
  • Clock path ECO and Data path ECO
  • Constraint Development specifically Interface timing

Synthesis and STA Training

  • Synthesis Training covers the aspect of converting the design in form of RTL into Technology mapped netlist. Synthesis is an algorithm intensive task consisting of many stages within it requiring various inputs in order to produce a functionally correct netlist. The main part of Synthesis Training consists of reading in the design, converting RTL to Boolean equations through elaboration, then converting the Boolean equations to Generic Mapped Cells and then technology mapped cells from library, setting constraints, optimizing the design, analyzing the results and saving the design database for Placement and Routing stage to take on. Candidates who are interested in exploring opportunities in Synthesis and Front-end STA can undergo this in-depth Synthesis training to get good understanding of RTL constructs, Gate level Netlist, Constraint Development, Latch based designs, pipe lining and re-timing, basic Scan stitching, Setup timing closure, Topography based logic re-structuring, Wire Load Models, Logical Equivalence Checks. Hierarchical Synthesis is another key feature covered in this Synthesis Training Cadence Implementation Suite for Synthesis (as RTL Compiler / Genus) would be used in this Synthesis Training program. Candidates would get hands on work on two full designs.

    Synthesis Training Topic covered(Also include this in sylubus)
    • Introduction to synthesis.
    • Reading RTL in HDL form, dotlibs, SDC
    • Different types of RTL constructs
    • Analyzing dotlib files
    • Elaboration and Generic Synthesis
    • Understanding DesignWare components and Logical Operators
    • Clock gating insertion for reducing Dynamic power post CTS
    • Creating list of dont_touch and dont_use cells
    • Technology mapped Synthesis and optimization
    • Scan Insertion techniques
    • Checking Design for number of instances, area estimate
    • Check clock reaching clock pins of flops, unclocked flops
    • Time borrowing concepts for latch based paths
    • Leakage variants of standard cells LVT, RVT, HVT
    • Constraints on logical hierarchy boundaries
    • Setting Max Transition, Max Capacitance, Max Fanout
    • Push down and pull up timing constraints
    • Master clocks and generated clocks in design
    • Estimating uncertainty values, input and output delays in SDC
    • False path, Multi cycle path exceptions.
    • Disabling timing loops in design
    • Logical Equivalence Checking fundamentals (Top level and Hierarchical)
    • Hand off database to PnR
    • Synthesis

      • Introduction to synthesis.
      • HDL Modeling
      • Synthesis flow
      • Constraining the design for timing, area, power
      • Synthesize the Design
      • Analyze & Debug the results .
      • Optimization techniques
      • Report generation
      • Save the results and generate interface files to other tools
    • Static Timing Analysis

      • Introduction to Static Timing Analysis
      • Understanding Delays & Libraries:
      • Constraining the design with SDC commands.
      • Timing Analysis of Different Paths
      • Analyzing Timing Reports
      • Timing Exceptions:
      • Operating Conditions
      • Check timing by loading different .libs
      • Post Layout STA:
      • Multi-Mode Multi-Corner Analysis (MMMC)
      • Cross Talk (SI) Analysis
      • Sign-off STA & ECO Flow
      • Practical STA Issues and Solutions
  • CourseSynthesis & STA Training
    Duration 8 weeks
    Next Batch 5- August
    Demo Session 5- August (11:00AM - 2:00PM)
    Registration 6- August
    Schedule Both Saturday & Sunday(11:00AM - 2:00PM India time)
    New batch starts every 8 weeks
    Fee INR 20000/- + Tax
    Tool Tempus(Cadence)
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access using VPN
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 20
    Assignments 24
    Placement support Interview opportunity in at least 6 companies
    100% job on completion of all assignments
    and scoring good grade in monthly evaluation test
    Trainer 17+ Years of experience in VLSI industry
    • What are the Course Prerequisites?

      • Expertise on Verilog
      • Exposure to Testbench component coding using Verilog
    • Does course cover practical sessions on SystemVerilog usage?

      • Each aspect of course is supported by lot of practical examples
      • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
      • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 8 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Course Material Shared:
    • DFT quick reference manual
    • DFT Checklist
    • DFT Tool user guide
  • Target Audience:
    • Verification engineers looking to learn advanced verification techniques
    • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in DFT domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on multiple complex module level projects