STA Training is designed to make the Engineer or Designer understand the complete Timing SignOff strategies for successful and confident Tape-Out of the Design to the Semiconductor Fabrication House. Since timing is the heart beat of any chip, thorough understanding of timing concepts, development of Timing constraints are given through this STA Training especially when it comes to Ultra Deep Sub-Micron Technologies such as 28nm, 20nm, 14nm, 10nm. There are multiple parameters that decide how the timing of a chip would be functioning like Transition times of Clock phases and Data Path signals, Process and Voltage and Temperature (PVT) variations, Crosstalk noise affecting functionality of the chip, Crosstalk Delay affecting timing of the chip, which will be covered in greater detail in this STA Training. Other topics such as Advanced OCV, requirement of Clock path tweaking to meet desired frequency of the Chip will be discussed extensively in this STA Training. Pessimism inclusion when design is taped-out has been a norm to avoid any Silicon surprises but for higher frequency Designs on lower technology nodes, pessimism beyond a limit could be an over-do in which case pessimism-Removal is done through Path-Based Analysis rather than Graph based Analysis. This topic is covered with fine clarity in this STA Training. Above all, the fundamental part of setup and hold time fixing covering the above points are the key aspects of this STA Training. Tools used are Cadence Analysis Tool (Encounter Timing System or Tempus) for this STA training. Candidates will get access to tool both at institute and has option to connect to servers from home using Secure VPN to work on two SignOff projects hands on.Fixing of timing violations based on Sign-Off analysis for Multi Mode Multi Corner though ECOs would be across the breadth of this STA Training. Objective of this STA training is to shape graduating Bachelor’s and Master’s degree studentsas well as Physical Design Engineers explore opportunities in Block Level as well as Full Chip STA.
Below are the STA Training topics.
SignOff STA Training topics :
- Fundamental Setup and Hold Timing Checks
- Timing Arcs across Design Instances
- Stage Delay covering Cell Delay and Net Delay
- Asynchronous Flop, recovery and removal checks
- Cross Clock Timing Analysis
- Interface Timing Analysis (between reg and IO)
- Clock group based timing analysis
- Crosstalk Delay and Crosstalk Noise
- Advanced On Chip Variation, CPPR
- Multi-Mode Multi-Corner timing analysis
- Graph Based and Path based analysis
- Timing DRC – Transition, Capacitance, Fanout fixes.
- Clock path ECO and Data path ECO
- Constraint Development specifically Interface timing