Below chart summarises various courses offered

  • All courses offered in both classroom and live online training
    • Online training sessions are live and interactive
  • All courses offered below 40K (tax included)
  • Individual courses shown in below chart are the various job roles in VLSI Design flow.

Below is the skill set required for various domains. student can opt for courses based on the skill set interesting for them.

VLSI Front end domain(pre-synthesis flow) is a programming based job role, requires good expertise with Digital Design, Verilog, SV, UVM and standard protocols(Ex: AXI, AHB, SPI, PCIe, etc). Student should opt for this course if they are interested in programming based jobs. Front end engineer also requires ability to read the design specification, comprehend the design behaviour and implement the same using Verilog and SV.

VLSI Back end domain(post-synthesis flow) is more technology and tool based flow implementation job role, requiring good expertise with device fundamentals, VLSI technology concepts, digital design and design flow implementation using EDA tools(Ex: ICC, Design compiler). Student should opt for this course if they are interested in above skill set, and particularly not interested in programming based jobs.

Choosing the right course

  • To start with, opt for training in either VLSI Front end domain or VLSI Back end domain. Both these course will have 1.5 months of basics training, after that main course can be selected.
  • Both front end and back end domains offer similar job opportunities. Student should choose a course based on their passion and interest rather than job opportunities.
  • All VLSI Front end and Back end domain courses have common 1.5 months training, except for one domain specific course during initial 1.5 months.
    • Opt for specific domain(RTL Design, Verification, PD, DFT, Layout etc) after 1.5 months training.
    • Option to switch to any other domain without paying any additional fee during initial 1 month of the course.
    • DFT flow happens in both pre and post synthesis flow, hence DFT placed under backend flow is only for convenience.


VLSI Engineer Common Skill set required (Student will be trained on all these aspects)

  • Strong Digital Design fundamentals
  • CMOS Basics
  • Linux OS
  • Any one scripting language (PERL/Python/TCL)
  • Exposure to any one text editor (Gvim, Nedit, Notepad++)
  • Revision management tools exposure
    • Clearcase, GIT, Perforce (any one of these)

VLSI Back end domain specific skill set

  • Device fundamentals (Below is just a summary, not a complete list)
    • Conductors, Insulators, Semiconductors
    • N-doping, P-doping
    • Diode, BJT, PMOS, NMOS, CMOS, FinFET
    • 2nd order effects
  • IC Fabrication
  • VLSI Technology concepts (not a complete list)
    • Resistor, Capacitor, Inductor
    • RC Circuit Analysis
    • Parasitic’s(R, C), Fan-out, Load
    • Various delay types
    • Clock generation, Skew, buffers
  • Tool Command Language (TCL)
  • Tool expertise (Based on domain)
    • ICC, PT, Design Compiler, StarRC, Redhawk, ICV, etc

Embedded Systems skill set required

  • C Programming
  • C++, Data structures
  • Micro controllers(ARM, PIC)
  • Peripheral protocols (SPI, I2C, CAN, UART, etc)

Training Lab sessions:

  • Each course has 4 days of lab sessions per week (apart from regular sessions). Below is number of lab days for each course.
    • Functional Verification Training
      • Verilog : 22 days
      • Digital Design: 8 days of practice sessions
      • SV : 44 days
      • UVM : 15 days
      • Scripting: 6 days
      • Linux : 4 days
      • Revision management : 2 days
    • RTL Design and Integration
      • Verilog : 22
      • Digital design : 8
      • CDC and Lint : 15 days
      • LEC : 8
      • Synthesis and STA : 12
      • Hands on project: 15
    • Physical Design : 70 days
    • DFT : 60 days
    • Custom Layout : 60 days

Course registration

Course Registration

VLSI Front end domain specific skill set

  • Reading Design Specifications, Comprehend the design architecture and functionality
  • Standard Protocols
    • On-chip protocols
      • Ex: AXI, AHB, APB, etc
    • Peripheral Protocols
      • Ex: PCIe, USB, I2C, SPI, etc
  • Hardware Description Languages(HDL)
    • Verilog or VHDL (Preferably Verilog)
  • Hardware Verification Language (HVL)
    • SV
    • UVM (not a HVL, it is a methodology)
  • Debug expertise

Course schedule & Start dates

  • VLSI Front end Courses
    • Course starts every 6 weeks
      • V, SV & UVM training during weekends
      • Other courses(Digital, ASIC flow, etc)) during weekdays
        • Students missing these sessions will get video access or will be offered back up sessions.
    • 5 months course
      • 1.5 months (Common course for all front end courses)
        • Verilog with 4 hands on projects
        • VLSI Design Flow (ASIC Flow)
        • Advanced Digital Design
      • Functional Verification Training
        • 2.5 months
          • Systemverilog with 3 hands on projects
          • Linux
          • PERL/Python Scripting
        • 1 month
          • UVM with 1 hands on project
          • SOC Design & verification concepts
          • Revision management
      • RTL Design and Integration Training
        • 3.5 months
          • RTL Integration concepts
          • CDC, Lint
          • LEC
          • Synthesis
          • STA
  • VLSI Back end courses
    • Course starts every 6 weeks
    • 5 months (DFT is 4.5 months course)
      • 1.5 months (Common course for all back end courses)
        • Device fundamentals (not for DFT)
        • Fabrication (not for DFT)
        • VLSI Technology concepts
        • Advanced Digital Design
        • Linux OS
        • Domain specific basic course
          • Introduction to basic concepts of specific domain(ex: PD, DFT, Layout, STA, etc)
      • 3.5 months
        • In depth training with multiple hands on projects

Institute facilities

  • Access to all recorded videos at institute premises
  • Access for missed session videos to watch at home
  • Access to tools for 12 months
  • Option to repeat the course

Evaluation tests

Evaluation Test link for various VLSI Courses


  • Institute does not give any commitment for the job, job opportunities is based on current job scenario.
  • Student continues to get job support till they get job, however institute does not commit on timelines.
  • Institute conducts evaluation test every 3 weeks, more opportunities based on performance in these tests.

Course schedule and demo videos

Click here for detailed course Schedule, each course has demo videos

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