Physical Verification training is a four months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a Physical verification engineer. Physical Verification course ensures that a fresher/experienced engineer is prepared on all the aspects of Physical Verification including DRCs, LVS, ERC, Antenna Checks, Latchup, Exposure to the Importance of reliability checks like EM and IR analysis Design for manufacturability (DFM)checks, Electrostatic discharge (ESD) path checks.
Course will consist of 70% exposure to hands on projects and 30% theory sessions.
Course includes training on ASIC flow, Advanced Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and Analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Course includes 20+ detailed labs & assignments covering all aspects of Physical Verification with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchhoff law’s, Diode-operation, CMOS operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures with detailed physical verification checks for the same.
ASIC Flow Overview
- Requirements
- Design specification & architecture
- RTL Coding
- RTL integration
- Functional verification
- Synthesis
- DFT
- Physical Design
- STA
- Custom Layout
- Physical Verification
- Post Silicon Validation
Advanced Digital Design
Essentials of UNIX/Linux
- Linux/UNIX OS, Shell
- Working with files, directories
- Commonly used commands
Semiconductor Basics
- Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor.
- Basic Passive and Active devices.
- Ohms law, Kirchoff laws
- Basic of circuit understanding
CMOS & FINFET Basics
- MOSFET Basics, Operations, few simple circuits & second order effects.
- MOSFET Detailed fabrication process.
- FinFET working, Fabrication, advantages & disadvantages.
Layout tool
- Layout Editor Tool
- Understanding the schematic symbols and parameters
- Creating and managing libraries and cell
- Commands for Layout editing.
- Commands for schematic editing.
- Verification : DRC and LVS
- Antenna effect, latchup, Electromigration, IR Drop
- Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
- Resistor, Capacitor layout techniques
- CMOS and BiCMOS layout techniques
- Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Physical Verification Concepts
- Design Rule Checks
- Layout Versus Schematic (LVS)
- Electrical Rule Checks (ERC)
- Antenna Checks
- Latch-up
- Reliability checks like EM and IR analysis
- Design for manufacturability (DFM)checks
- Electrostatic discharge (ESD) path checks
Physical Verification Hands on projects
- Multiple projects with detailed Physical verification analysis
Assignments and hands on projects
- Assignments and multiple hands on projects
- Best Practices & Interview Questions.
| Course | Physical Verification Training | |
|---|---|---|
| Duration | 14 weeks | |
| Next Batches | 04/May, 08/June | |
| Demo Session | 04/May (8:30AM – 12:00PM) | |
| Registration | 05/May | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). | ||
| Weekdays sessions will be focused on training on device fundamentals – Digital Design – UNIX and TCL scripting. | ||
| Working professionals | Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US) | |
| 8:30AM – 12:30PM (Theory session offered by trainer) | ||
| 1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time. | ||
| Students will take the weekday tests and assignments from home. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| New batch starts | Every 5 Weeks | |
| Fee | ||
| PV Main Course | INR 26000 (All inclusive) (Classroom training) INR 32000 (All inclusive) (Online training) | |
| PV Basics Course | INR 8000 (All inclusive) (Course on Physical verification basics + TCL + Unix) INR 5000 (if this course is taken along with Physical Verification main course above) | |
| Tool | Synopsys Custom compiler, IC Validator | |
| Mode of training | Classroom training at VLSIGuru Institute, ORR, Banaswadi | |
| Online training using live training sessions | ||
| Tool Access | Tool access for 12 months at the institute | |
| Certificate | Issued based on 50% assignment completion as criteria | |
| Batch Size | 20 | |
| Assignments | 10 | |
| Evaluation tests | 10(evaluation test followed by discussion on same). | |
| Admission criteria | Student need to undergo evaluation test based on basic digital and Device fundamentals. (1 Hour duration) | |
| Placement support | Interview opportunity in at least 6 companies | |
| Trainer | 5+ Years of industrial experience |
What are the Course Prerequisites?
- Expertise on Digital & Analog design concepts
- Exposure to basic layout concepts
Course Material Shared:
- User Manual
- Layout Checklist
- Tool user guide
Trainer Profile
- 5+ years of rich experience of working in all aspects of custom layout & Physical verification.
