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Physical Verification Training

Physical verification is a process whereby an integrated circuit layout (IC layout) design is checked via EDA software tools to see if it meets certain criteria. Verification involves design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), XOR (exclusive OR), and antenna checks.

Physical verification training will focus on all aspects of physical verification including XOR check, ANtenna check and ERC.

Physical Verification Training

  • Physical verification is a process whereby an integrated circuit layout (IC layout) design is checked via EDA software tools to see if it meets certain criteria. Verification involves design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), XOR (exclusive OR), and antenna checks.

    • Physical Verification Training

    • Next Batch: 3/Sep, 2:00PM - 6:00PM
    • Duration: 8 Weeks
    • Fee : INR 12,000
    • Tools : Tessent FastScan(Mentor Graphics)
    • Access to tool using remote connection
    • Certificate of course completion
    • Options to repeat the course

    Registration:
    • Attend Demo Session on 3/Sep, 2:00PM-6:00PM
    • Registration on 4/Sep

    • What are the Course Prerequisites?

      • Expertise on Verilog
      • Exposure to Testbench component coding using Verilog

    • Does course cover practical sessions on SystemVerilog usage?

      • Each aspect of course is supported by lot of practical examples
      • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
      • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch

    • Is it possible to cover so many things in 8 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts

    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared

    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year

    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Course Material Shared:
    • DFT quick reference manual
    • DFT Checklist
    • DFT Tool user guide
  • Target Audience:
    • Verification engineers looking to learn advanced verification techniques
    • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in DFT domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on multiple complex module level projects
Quality VLSI Training at Affordable Fee.

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