Mentor Graphics Tessent flow is the de-facto standard for DFT flow with 80% of market share. Would you go with any other tool flow for DFT training?
Design For Testability
DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.
DFT Training will focus on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.
As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.
DFT Basics course syllabus(6 weeks)
VLSI Design flow
- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
Advanced Digital Design
- Digital Design basics
- combinational logic
- sequential logic, FF, latch, counters
- Memories
- Setup time, Hold time, timing closure, fixing setup time and hold time violations
- STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
- www.vlsiguru.com/digital-design-complete
Linux operating system
- Shells
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
- Makefiles
TCL Scripting
- Introduce TCL
- Why TCL?
- TCL Script Processing
- Understand TCL uses and strengths
- Writing simple TCL scripts
- TCL for VLSI scripting
- TCL : Main Features
- TCL in EDA
- TCL shell (tclsh)
- Working with TCL scripts (UNIX)
- TCL Interpreter in SoC Design Tools
- TCL Scripting for SoC Design
- TCL Commands
- Variables
- Substitution and Command Evaluation
- Operators
- Mathematical Functions
- Procedures
- Control flow : if, if-else, switch, for, foreach, while, break and continue
- string, string operations
- List, List manipulation
- Arrays, array methods
- Working with files
- Command line arguments
- Regular expressions
- Complete TCL Scripts
- TCL Packages
Verilog basics
- Verilog language constructs
- Combinational logic implementation using Verilog
- Testbench coding for combinational logic
- Sequential logic implementation using Verilog
- Testbench coding for sequential logic
- Clock generation with frequency , Jitter and duty cycle
- Memory coding and test bench setup
- Running simulations, analysing waveforms, debugging concepts
DFT main course syllabus (16 weeks)
Design For Testability (Below is DFT Main course weekly schedule)
- DFT Basics
- SoC Scan architecture overview
- Types of Scan
- ATPG DRC Debug
- ATPG Simulation Mismatch Debug
- DFT Diagnosis
- JTAG
- MemoryBIST
- LogicBIST
- Scan and ATPG
- Test compression technigues
- Hierarchical Scan Design
Week1
- Introduction to DFT
- Roles in DFT
- Full SOC flow – DFT
- DFT Architecture and Basics
- Test Plan
- Different DFT schemes
- Comparison between Functional and DFT Vectors
- Defect, Fault and Error
- Revision of Digital Concepts
Week-2
- Understanding of SCAN Insertion
- Scan methodology
- Types of Scan
- Top-down and Bottom-up Approach
- Scan insertion Flow
- Scan operation
- Clocking structure relation in SCAN
- DFT rule checks – Clock and Reset
Week-3
- Scan insertion Scripts
- Multiple Clock domains
- DFT Rule Checks – Advanced (Tristate, PRC, XS)
- Precautions for building a proper scan chain
- Edge and Domain Mixing significance
- Scan Configurations
- Scan chain Balancing
- Lock up and Terminal lockup latches
- Hands-on Scan insertion
- Explanation about Netlist and Library files
- Assignments
Week-4
- Hook-Up Scan sub chains
- Introduction to compression
- Compression Architecture
- Decompressor and Compactor
- LFSR
- Compression Ratio
- Masking Logic
- One hot Decoder
- Internal scan chains
- DRC Analysis
- Scan Reorder
- Control signals
Week-5
- Modular Compression
- Introduction to Synthesis
- Hands-on Compression
- Assignments
- ATPG Tools Introduction
- Fault Models
- Fault Categories
- Algorithms used in ATPG
Week-6
- ATPG Flow
- Coverage Analysis
- Fault Classes
- ATPG DRC’s
- Hands-on Stuck-at ATPG
- Assignments
Week-7
- Concepts related to STA – Basics
- MCP and FP
- Reports of ATPG
- Sequential Depth
- Transition delay faults (TDF)
- Path delay faults (PDF)
- Hands-on TDF ATPG
Week-8
- Types of patterns
- Formats of patterns
- Fault grading
- LOC , LOS and LOES
- On chip clock control
- Advantages
- Dis-advantages
- Internal structure
Week-9
- Introduction to Validation
- Simulations flow
- Tools for simulation
- Simulation mismatches debug
- No timing and Timing based Simulations
- Hands-on Simulations
Week-10
- Flat Models
- Introduction to JTAG/IJTAG
- Introductions to PADS
- BS Insertion
- JTAG/IJTAG FSM
- Instructions of JTAG/IJTAG
Week-11
- Introduction to MBIST
- Memory faults
- Memory grouping
- Memory basics
- Algorithms
- Zero-one, CHBK , MATS .MARCH ,SMARCH ..etc
- MBIST Insertion on RTL
- Hands on BIST insertion
- Assignments
Week-12
- Discussion of Interview questions
- Compactor explanation
- Memory pipelining
- ET flow
- Hierarchical BIST insertion
- Hands of multi core MBIST insertion
- Assignments
Week-13
- Complete Flow of BIST insertion and validation
- Clock Monitoring
- ICL network
- EDT and OCC insertion on RTL
- Gray box generation
- Assignments
Week-14
- Introduction to ICL and PDL
- Scan Wrapper insertion – Hierarchical Flow
- Intest and Extest Hands on Lab sessions
- Assignments
- ATPG Flow with TSDB
- Faults merging
WEEK-15
- Controlling PLL and CLK Gen’s using ICL and PDL
- Introduction to BISR
- Auxiliary Pins
- Revision of JTAG/IJTAG and BIST concepts
WEEK-16
- Support for Mock interviews
- Interactive sessions
- Complete Revision of DFT as follows:
- DFT Overview
- SCAN
- COMPRESSION
- OCC
- JTAG/IJTAG
- MBIST/MBISR
- ATPG
- SIMULATIONS – ATPG and BIST
- Handling third party IP’s for DFT
- DFT Insertions in both RTL and NETLIST
- Total 4 levels of Projects in the entire course duration. Each Level contains 5-10 Working Labs.
| Course | DFT Training |
|---|---|
| Duration | 22 weeks (6 weeks of basics training, 16 weeks of core DFT training) |
| Next Batch | 07/MAY |
| Schedule | Weekend batch: Saturday & Sunday(9AM – 5PM India time) Full week batch: 6 days/week, 9AM – 1PM, Friday is break |
| Course repeats | every 8 weeks |
| Tool | Mentor Graphics Tessent, Synopsys DFTAdvisor and Tetramax |
| Mode of training | Both Classroom training and live online training |
| e-learning course for self paced learning | |
| Tool Access | Tool access for the complete course duration |
| Certificate | Issued based on 50% assignment completion as criteria |
| Batch Size | 15 |
| Assignments | 20 |
What are the Course Prerequisites?
- Course does not have any pre-requisites. However any exposure to Digital design, VLSI design flow is an added advantage.
What if I miss few sessions during course?
- Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
| DFT Course Material | Access |
|---|---|
| Course material | Shared over google drive |
| Course page access | Get login details from Admin |
| Assignments-Checklist-Session notes | Course page |
| Labs | Copy labs from /home/vlsiguru/DFT/ to /home/user_ID/ Refer to README files in individual folders. |
| Labs are available for Scan-compression-JTAG-BIST and pattern simulations. | |
| How to use course material | Shared as part of Course material |
| Resume update | Course page |
| Interview Questions | Uploaded to course page |
- Trainer Profile
- 12+ years experience
- Experience of working on multiple complex SOC projects
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- Fee: INR 45,000 + GST
- Confirm your course enrolment by making 5,000 INR transfer to below account.
- Payment schedule
- 5000 INR towards course enrolment
- 40000 + GST(overall)
- Half payment within 1 week of course commencement
- Remaining half within 1.5 month