DFT(Design for Testability) involves using SCAN, ATPG and BIST techniques to add testability to Hardware design. These techniques are targeted towards making it easier to develop and apply tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, etc.

DFT Training will focus on all aspects of testability flow including testability basics, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests.  ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.

DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression and ATPG pattern generation using MentorGraphics Tessent tool.  More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.

MentorGraphics Tessent tool will be used for training. As per survey, it is used by more than 80% companies for DFT. Student will have access to tool for during the course, with provision to extend beyond. Student will get access to tool both at institute and has option to connect to servers from home using VPN.

Student will also get access to Synopsys tool suite.

Design For Testability

Overview

DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted towards making it easier to develop and apply tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.

DFT Training will focus on all aspects of testability flow including DFT basics,  various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.

DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.

MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.

Syllabus

VLSI Basics Course (4 weeks)

  • ASIC Flow
  • Advanced Digital Design
  • Verilog programming basics
  • Linux OS
  • TCL Scripting

Design For Testability (Below is DFT Main course weekly schedule)

  • DFT Basics
  • SoC Scan architecture overview
  • Types of Scan
  • ATPG DRC Debug
  • ATPG Simulation Mismatch Debug
  • DFT Diagnosis
  • JTAG
  • MemoryBIST
  • LogicBIST
  • Scan and ATPG
  • Test compression technigues
  • Hierarchical Scan Design

Week-1

  • Full SOC flow – DFT
  • DFT Architecture and Basics
  • Test Plan
  • Different DFT schemes
  • Comparison between Functional and DFT Vectors

Week-2

  • Understanding of SCAN Insertion
  • Scan methodology
  • Types of Scan
  • Top-down and Bottom-up Approach
  • Scan insertion Flow
  • Scan operation

Week-3

  • Scan insertion Scripts
  • Multiple Clock domains
  • Design Rule Checking
  • Pre-DRC and Post DRC
  • Lock up and Terminal lockup latches
  • Hands-on Scan insertion
  • Assignments
  • Interaction Sessions

Week-4

  • Introduction to compression
  • Compression Architecture
  • Decompressor and Compactor
  • Compression Ratio
  • DRC Analysis

Week-5

  • Modular Compression
  • X-Masking logic
  • Hands-on Compression
  • Assignments
  • Interaction Sessions

Week-6

  • Scan insertion with compression
  • On-chip clocking for at-speed testing
  • Hierarchical Scan Design
  • Bypass mode
  • Hands on Scan and compression
  • Interaction session scan and compression

Week-7

  • Introduction to MBIST
  • Memory grouping
  • Controller generation
  • Memory faults
  • Algorithms
  • Diagnostic mode

Week-8

  • ATPG Overview
  • Different types of Faults
  • Types of fault models
  • ATPG algorithm
  • Understand complete Test procedure
  • Hands on Project

Week-9

  • DRC analysis
  • Test Coverage and Fault Coverage
  • Coverage improvement Analysis
  • Chain and Capture patterns
  • Assignments
  • Interaction Sessions
  • Simulations- Notiming and Timing simulations

Week-10

  • At speed fault model (In detail)
  • Understanding Transition fault ATPG
  • Two pulse generator
  • Test procedure
  • Launch on capture and Launch on Shift
  • Top-off Pattern generation
  • Path delay

Week-11

  • Introduction to JTAG
  • JTAG State Machine
  • Boundary Scan
  • Different instructions
  • Industry Standard Project

Week-12

  • Introduction to LBIST
  • SPYGLASS
  • Revision
  • Mock Interview

Schedule

Course DFT Training
Duration 18 weeks
Next Batch 2/Nov
Demo Session 2/Nov (9AM – 12:30PM)
Course Enrol 3/Nov
Schedule Both Saturday & Sunday(9:00AM – 4:30PM India time)
Course repeats every 8 weeks
Fee INR 39000 (Classroom training), INR 45000 (online training), Fee is all inclusive
Tool Mentor Graphics Tessent, Synopsys DFTAdvisor
Mode of training Classroom training at VLSIGuru Institute(Horamavu)
Online training using live training sessions
Tool Access Tool access at the institute for one year duration
Certificate Issued based on 50% assignment completion as criteria
Admission criteria Student need to undergo evaluation test
Batch Size 20
Assignments 20
Placement support Interview opportunity in at least 6 companies.
Trainer 12+ Years Exp.

DFT weekly Schedule

FAQs

What are the Course Prerequisites?

  • Exposure to Basic Scan concepts

What if I miss few sessions during course?

  • Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

Course Material

DFT Course Material Access
Course material Shared over google drive
Course page access Get login details from Admin
Assignments-Checklist-Session notes Course page
Labs Copy labs from /home/vlsiguru/DFT/ to /home/user_ID/ Refer to README files in individual folders.
Labs are available for Scan-compression-JTAG-BIST and pattern simulations.
How to use course material Shared as part of Course material
Resume update Course page
Interview Questions Uploaded to course page

Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.

Session Notes Link
WEEK1 DFT BASICS Click here
WEEK2 SCAN INSERTION Click here
WEEK3 SCAN INSERTION Click here
WEEK4 Click here
WEEK5 Click here
WEEK6 Click here
WEEK7 MBIST Click here
WEEK8 ATPG Click here
WEEK9 Click here
WEEK10 ATSPEED Click here

 

ASSIGNMENTS Link
BASIC DFT Click here
SCAN Click here
COMPRESSION Click here
MBIST Click here
ATPG Click here
SIMULATIONS Click here
JTAG Click here

 

LAB ASSIGNMENTS Link
SCAN Click here
ATPG Click here

 

PRESENATATIONS Link
DFT Basics Click here
SCAN INSERTION PART1 Click here
SCAN INSERTION PART2 Click here
COMPRESSION Click here
MBIST Click here

 

LAB INSTRUCTIONS Link
ATPG Click here
SCAN Click here

Audience

  • Target Audience:
    • BTech, MTech Freshers planning to make career in DFT
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in DFT
    • Engineering college faculty looking to enhance their VLSI skill set

Trainer

  • Trainer Profile
    • 12+ years experience
    • Experience of working on multiple complex SOC projects
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