VLSI Functional verification

1-1 training Highlights

Course content - Hourly breakup

Topic Duration(Hours)
Number systems, radix conversions 1
K-maps, min terms, max terms, POS and SOP 1
Logic gates, realization of logic gates using mux and universal gates 1
Compliments (1/2/9/10’s complement), Arithmetic operations using compliments 1
Boolean expression minimization, D-morgan theorems 1
Adders – Half adder, Full adder, Subtractors Half subtractor, Full subtractor 1
Adders and subtractors using Mux’s 1
Multiplexers – Realizing bigger Mux’s using smaller Mux’s 1
Decoders and Encoders, Decoders and Encoders using Mux and Demux 1
Bigger Decoder/Encoder using smaller Decoder/Encoder 1
Comparators, multi bit comparators using 1 bit comparator 1
Latch, Flipflop – realization using Gates or Mux’s 1
Different types of FFs – Excitation tables 1
Applications of FF’s, Latches – Counters, Shift registers 1
Synchronizers for clock domain crossing 1
FSM – Mealy, Moore FSM 1
FSM – Mealy, Moore FSM implementation using different types of FFs 1
Frequency dividers, Frequency multiplication 1
Total 18
TopicDuration(Hours)
Verilog constructs2
Combinational logic implementation5
Sequential logic implementation3
Advanced Verilog language constructs10
Verilog projects 
Memory verilog coding and TB development3
Synchronous and Asynchronous FIFO design and verification4
SPI Controller4
Pattern detector2
CRC generation2
Total35
TopicDuration(Hours)
Data types, operators, arrays6
Object oriented programming12
Interface, program, Inter process synchronization3
Constraints and randomization4
Functional and code coverage4
Assertions3
Other SV language constructs3
SV Test bench setup for memory5
Total40
Topic Duration(Hours)
UVM base classes, UVM TB hierarchy 3
Root, objections, phases, Command line processor 3
Reporting classes 2
UVM config DB and Resource DB, Factory 3
TLM1.0 2
Sequences, sequence library 2
RAL, register model coding 3
UVM Test bench setup for memory 4
Total 22
TopicDuration(Hours)
SPI Protocol0 (already covered in Verilog)
I2C Protocol2
APB protocol1
AHB protocol4
AXI protocol5
Total12
TopicDuration(Hours)
AXI VIP development using SV & UVM6
Ethernet MAC functional verification using SV & UVM24
Total30
Topic Duration(Hours)
Linux basic commands – File and directory handling 1
Linux advanced commands – sed, awk, grep, xargs 2
Python variables, Lists, tuples, dictionaries 1
Operators, loops, working with files 2
Regular expressions, Python hands on examples 2
Total 8

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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