1. Explain various steps involved VLSI Design flow from requirements to packaging
  2. List down the inputs required for each stage of VLSI Design flow
  3. VLSI Design flow has various types of verification/validation as below, list down significant differences among these.
    1. Functional verification
    2. Formal verification
    3. Physical verification
    4. Post silicon validation
    5. Timing closure(STA)
    6. Gate level simulations
    7. Assertion based verification
  4. What is DFT, explain different types of DFT techniques. What type of faults does it catch?
  5. What is lint checks? Which tool is used for the same? What stage of VLSI flow is it done?
  6. List down various EDA tools used in different stages of VLSI flow.
    1. Ex: Spyglass used for lint checks during RTL Design phase, etc
  7. How do we ensure that synthesized netlist is functionally matching the RTL code behavior?
  8. What is SDF? What do we mean by SDF annotation? Who generates the SDF files? Where is it used? List down various types of delays in chip
  9. STA & Gate level simulations are used for checking setup and hold time violations, why should we do both, if both are meant for same purpose?
  10. What is the difference between pre-layout STA and post layout STA?
  11. What is the significance of Standard cell library? Which aspects of VLSI flow requires these?
  12. What is a testbench? List down various components of testbench and write the significance of each of the components.
  13. What is Physical design? What are various steps involved in Physical design flow?
  14. What is the significance of GDSII in VLSI flow
  15. The synthesized output is called netlist, what is the reason for this naming?
  16. What is the difference between behavioral verilog code and gate level netlist?
  17. List down various components and subsystems in a typical Mobile phone SOC
  18. What is NOC, list down various types of NOC’s in a complex SOC
  19. What does PVT stand for. What is the significance in timing closure.
  20. What is the significance of test patterns in post silicon validation
  21. List down various categories of test cases used in functional verification flow
  22. List down the reasons why industry is moving from BJT to CMOS to FinFET for lower nodes.(14nm and below is FinFET)
  23. What is base tapeout and metal tapeout?
  24. What is low power verification? Why SOC is divided in voltage domains, power domains and clock domains?
  25. What is the significance of global clock controller and how clock routing works in SOC
  26. List down various types of SOC platforms in VLSI industry?
    1. ex: Networking chips, mobile SOC, etc
  27. List down atleast 10 processors used in various SOC
    1. Ex: Cortex A57 from ARM
  28. What is interrupt mapping? Why is it important
  29. What is address mapping? Significance?
  30. If a chip fault or functional issue is detected at post silicon validation checks, how is it fixed? What is RMA? What is ECO?
  31. List down at least 10 features of a mobile phone SOC that architect uses as input to develop architecture.
  32. What is Scan flop, what is the significance? What is scan chain?
  33. How ASIC flow differs from FPGA flow?
  34. What do we mean by Synthesizable RTL code?
  35. List down atleast 5 on-chip communication protocols and 5 peripheral communication protocols used in various chips
  36. Assuming mobile phone SOC flow takes 1 year time, write the timeline and various stages performed during this?
    1. ex: Architecture: 1st month
    2. RTL coding: starts in 1st month, alteast goes for 3 months


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