SESSION#1
status:
agenda:
SESSION#2
5.
switch(sel)
2’b00 : y = i0;
2’b01 : y = i0;
8.
reg [2:-2] addr;
reg [-6:-2] addr;
module processor(clk, rst, valid, ready, wr_rd, addr, wdata, rdata);
input clk, rst, ready;
output valid, wr_rd;
output [7:0] addr;
output [15:0] wdata;
input [15:0] rdata;
endmodule
module memory(clk, rst, valid, ready, wr_rd, addr, wdata, rdata);
input clk, rst;
output ready;
input valid, wr_rd;
input [7:0] addr;
input [15:0] wdata;
output [15:0] rdata;
endmodule
module memory(input clk, input rst, input valid, output ready, input wr_rd, input [7:0] addr, input [15:0] wdata, output [15:0] rdata);
endmodule
11.
addr = 32’d200;
represent the smae in all radix formats:
Octal => addr = 32’o310
Hexa => addr = 32’hC8
Bindary => addr = 32’h1100_1000
12.
reg [31:0] data
data = 32’h1F2F_3F4F;
data = 32’b10101001_0101_0101_0101_0010_1010;
Octal:
8’b10_10x_xxx
8’o2Xx
Decimal: X
14.
Value = 350 decimal, Size = 15
represent in all formats.
350 : Hexa
256 + 64 + 16 + 8 + 4 + 2
101011110
16.
What EDA stands for?
What are the steps involved in implementing a design using gates?
What is meant by higher level description?
How Hardware differs from a software?
Why C/C++ are not suitable for hardware description?
How Verilog represents concept of structure?
How Verilog represents concept of time?
How Verilog represents concept of concurrent running process?
What is the IEEE standard for Verilog?
How many IEEE Verilog versions are there?
Why Verilog is preferred over VHDL?
Write Verilog code of Synchronous DFF?
Write Verilog code of active low reset Asynchronous DFF?
Write Verilog code for 4X1 Mux?
How to check if Verilog code is working as expected?
Write Verilog code for 3 bit FA?
What are various steps in Verilog code execution?
What are various abstraction levels in Verilog?
What is meant by Literals?
What are the examples of Verilog literal value set?
Why do we need ‘x’?
Why do we need ‘z’?
reg addr; is it scalar or vector?
reg [3:0] valid? scalar or vector?
represent 578 using 10 bit size in all radix format?
reg [-3:3] vec_a, reg [7:1] vec_b, vec_a = vec_b, what is the mapping?
if vec_b value is 125, what is vec_a[2]?
what is octal equivalent of following?
xxx, xzx, x0x, z0z, 1zx, zzz, 101
What is the default radix if not specified?
if vec_b value is 125, what is vec_a[2]?
vec_b = 1111101
vec_a = 1111101
vec_a[1:3] = 3'b101
reg [10:3] vec_a, reg [7:1] vec_b = 69;
vec_a = vec_b
what is vec_a[7]
what is vec_a[10:8]?
what is vec_a[5:3]?
reg [12:3] vec_a, reg [9:1] vec_b,
vec_a = vec_b
vec_b = -69
vec_b = 9’b11011_1011
what is vec_a[7]
what is vec_a[10:8]?
what is vec_a[5:3]?
what is vec_a[12:8]?
reg [12:3] vec_a, reg [9:1] vec_b = -95;
vec_a = vec_b
what is vec_a[7]
what is vec_a[5:3]?
what is vec_a[12:8]?
19.
Question
reg [3:0] a, b, c;
a=9, b=7, c?
SESSION#3
Questions:
Notes:
2 bit signed variable: -2 to 1 (-2,-1,0,1)
3 bit signed variable: -4 to 3 (-2,-1,0,1)
-2(n-1) <—> 2(n-1)-1
byte: 8 bit signed variable: -128 to 127
integer: 32 bit signed variable: -231 to 231 – 1
SESSION#4
vector can only be off reg/wire data type.
integer [3:0] intvec; //NOT possible
integer intArr [3:0]; //possible
SESSION#5
8.
Result is ONE bit value: 0, 1 or x
A = 6; A && B 1 && 0 -> 0 (logically false)
B = 0; A || !B 1 || 1 -> 1
C = x; C || B x || 0 => x, c && b = 0
A is logically true, B is logically false
C is logically unknown.
A = true
B = false
C = unknown
A && B = true && false = false = 0
A || B = true || false = true = 1
A || !B = true || true = true = 1
C || B = unknown || false = unknown
C || !B = unknown || true = true
x | 1 = 1
9.
module tb;
reg [9:0] a;
initial begin
a = -9;
~a
10.
Homework
a = b << c;
in above, what is operator and what are operands?
how shift operator makes multiplication easier to implement?
what is the difference between logical not and bitwise inversion?
a = -1, b = 1, c = a && b; what will be c?
a = -1, b = 1, c = a & b; what will be c?
size needs to be provided, assume integers.
a = -7, b = 11, both are integers, what is a & b?
real a; integer b; real c;
a = 3; b = 10; c = b/a; what will be value of c?
reg [5:0] a; reg [-2:-1] b; reg [5:0] c;
a= 95;
b = 69;
c = a & b; what will be c?
c = a | b; what will be c?
How unary reduction operators make vector analysis easier?
how the operator usage differs between vectors and arrays?
We have a register which is 16 bits, we want to always write [7:4] as always 4’b1111, irrespective of other bit values, how can we implement this using bitwise operators
List down various types of operators in Verilog
reg [7:0] a = -25
what is b = a >> 2;
a = 00011001
-25 = 11100111
-25>>2 = 00111001 = 57
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