SESSION#1

status:

• 2×1 mux, 4×1 mux
  o gate level
  o behavioral
  o how to generate random inputs

agenda:

1. combinational logic
   o how to implement structural modeling
2. 4×1 mux using 2×1 mux
   o concept of creating a bigger module(structure) using already existing modules(structure) => structural modeling.
3. To implement combinational logic => dataflow modeling is the preferred style of coding.
4. any line that ends with ; is called as statement
   any statment inside always or initial block => procedural statement
   any variable on the LHS of any procedural statement => compolsory ‘reg’, everything else is ‘wire’
5. combinational circuits
   • comparator
   • encoder
   • decoder
   • priority encoder
   • subtractor
   • binary to gray code converter
   • excess-3

SESSION#2

1. encoder using 2×1 mux
   Q1 = D2 | D3
2. Decoder
   truth tbale -> k-maps -> expression
3. 2×4 decoder
4. 10×1024 decoder
   truth table -> k-maps -> expression
   • this apprach is complex
     • truth table will have 1024 entires
     • implement k-map is very difficult
     • coming with expression is difficult
5. Verilog
   3- bit up counter

5.
switch(sel)
2’b00 : y = i0;
2’b01 : y = i0;

6. x is required for representing unknown value
   o when do we some circuit output as unknown?
   o inputs are x or z
   o setup or hold timing violations in Flipflop
7. Size = 7
   LSB = 3
   name = addr
   reg vector
   reg [9:3] addr;
   reg [-3:3] addr;

8.
reg [2:-2] addr;
reg [-6:-2] addr;

9. reg addr0, addr1, addr2, addr3…a31;
   reg [31:0] addr;
   addr[15] => we refer to 15th bit of addr.
10. processor – memory connection
    addr :
    wr_data :
    rd_data :
    wr_rd : 1 (write), 0 (read)
    valid = 1 => Processor is doing a valid transaction to the memory
    = 0 => Processor is not doing a valid transaction to the memory
    ready = 1 => memory is ready to respond to the processor request
    = 0 => memory is not ready to respond to the processor request
    clk, rst scalar: clk, rst, valid, ready, wr_rd
    vector: addr, wdata, rdata

module processor(clk, rst, valid, ready, wr_rd, addr, wdata, rdata);
input clk, rst, ready;
output valid, wr_rd;
output [7:0] addr;
output [15:0] wdata;
input [15:0] rdata;

endmodule

module memory(clk, rst, valid, ready, wr_rd, addr, wdata, rdata);
input clk, rst;
output ready;
input valid, wr_rd;
input [7:0] addr;
input [15:0] wdata;
output [15:0] rdata;

endmodule

module memory(input clk, input rst, input valid, output ready, input wr_rd, input [7:0] addr, input [15:0] wdata, output [15:0] rdata);

endmodule

11.
addr = 32’d200;
represent the smae in all radix formats:
Octal => addr = 32’o310
Hexa => addr = 32’hC8
Bindary => addr = 32’h1100_1000

12.
reg [31:0] data
data = 32’h1F2F_3F4F;
data = 32’b10101001_0101_0101_0101_0010_1010;

13. 
    8’hax
    x : all 4 x’s
    8’b1010_xxxx

Octal:
8’b10_10x_xxx
8’o2Xx

Decimal: X

14.
Value = 350 decimal, Size = 15
represent in all formats.

350 : Hexa
256 + 64 + 16 + 8 + 4 + 2
101011110

15. Represent 16’hCxDz in all radix formats.
    16’b1100_xxxx_1101_zzzz
    16’b1_100_xxx_x11_01z_zzz
    16’o14xXZz

16.
What EDA stands for?
What are the steps involved in implementing a design using gates?
What is meant by higher level description?
How Hardware differs from a software?
Why C/C++ are not suitable for hardware description?
How Verilog represents concept of structure?
How Verilog represents concept of time?
How Verilog represents concept of concurrent running process?
What is the IEEE standard for Verilog?
How many IEEE Verilog versions are there?
Why Verilog is preferred over VHDL?
Write Verilog code of Synchronous DFF?
Write Verilog code of active low reset Asynchronous DFF?
Write Verilog code for 4X1 Mux?
How to check if Verilog code is working as expected?
Write Verilog code for 3 bit FA?
What are various steps in Verilog code execution?
What are various abstraction levels in Verilog?
What is meant by Literals?
What are the examples of Verilog literal value set?
Why do we need ‘x’?
Why do we need ‘z’?
reg addr; is it scalar or vector?
reg [3:0] valid? scalar or vector?
represent 578 using 10 bit size in all radix format?
reg [-3:3] vec_a, reg [7:1] vec_b, vec_a = vec_b, what is the mapping?
if vec_b value is 125, what is vec_a[2]?
what is octal equivalent of following?
xxx, xzx, x0x, z0z, 1zx, zzz, 101
What is the default radix if not specified?

17. reg [-5:-8] vec_a;
    reg [7:11] vec_b;
    vec_a = vec_b;
    write individual copies?
    vec_a[-8] = vec_b[11];
    vec_a[-7] = vec_b[10];
    vec_a[-6] = vec_b[9];
    vec_a[-5] = vec_b[8];
    otehr bits of vec_b are ignored.
18. Hoemwork
    reg [-3:3] vec_a, reg [7:1] vec_b,
    vec_a = vec_b, what is the mapping?

if vec_b value is 125, what is vec_a[2]?
vec_b = 1111101
vec_a = 1111101

vec_a[1:3] = 3'b101

reg [10:3] vec_a, reg [7:1] vec_b = 69;
vec_a = vec_b
what is vec_a[7]
what is vec_a[10:8]?
what is vec_a[5:3]?

reg [12:3] vec_a, reg [9:1] vec_b,
vec_a = vec_b
vec_b = -69
vec_b = 9’b11011_1011
what is vec_a[7]
what is vec_a[10:8]?
what is vec_a[5:3]?
what is vec_a[12:8]?

reg [12:3] vec_a, reg [9:1] vec_b = -95;
vec_a = vec_b
what is vec_a[7]
what is vec_a[5:3]?
what is vec_a[12:8]?

19.
Question
reg [3:0] a, b, c;
a=9, b=7, c?

SESSION#3

Questions:

1. xzx => 12 bit
   binary: xxxx_zzzz_xxxx
   octal: xxx_xzz_zzx_xxx
   octal: 12’oxXXx

Notes:

1. integer range

2 bit signed variable: -2 to 1 (-2,-1,0,1)
3 bit signed variable: -4 to 3 (-2,-1,0,1)
-2(n-1) <—> 2(n-1)-1

byte: 8 bit signed variable: -128 to 127
integer: 32 bit signed variable: -231 to 231 – 1

4. homework
   o print default values of integer and real, check x and 0 values
5. `timescale time_step/time_precision
   analogy:
   • grnd floor -> 1st floor
     15 feet
     if we go 1 feet at a time => time_step = 1 feet
     if we can see the things up to 1 cm precision: => time_precision = 1 cm
     `timescale 1feet/1cm
   • how does it complete the simulation events?
     o time step
   • climbiming at 1cm at a time, 15feet
     o 15*30 = 450 steps => it slows down my clibming
     => if we use very small timestep => it can slow down simulation.
6. How electronic devices use clock to measure teh time.
   o 1 second
   o clock = 1Mhz
   o 1/1Mhz = 1 micro second (Time period) => time difference between one +edge to negative
   one +edge can measure=1us
   how many edges required to measure 1sec
   1sec/1us = 10**6
7. Traffic light controller working at 10KHz (0.1ms or 10-4sec) Red time=10sec, Yellow=20sec, Green=50sec Clock cycles required to measure Red time = 105 (10/10-4 = 105)
   Clock cycles required to measure Green time = 510*5
8. 10Mhz clock, number of cycles to measure 2 sec?
   2107 10Mhz = 107Hz = 10-7 sec 2 sec => 2 sec/10-7 sec = 210**7
9. TP=10us
   frequency in terms of Mhz? 0.1Mhz
   TP = 10us = 1010-6 sec = 10-5 sec = 105 Hz convert Hz to Mhz=> 105/10*6 = 0.1MHz frequency in terms of Khz? 0.11000Khz = 100Khz frequency in terms of Ghz? 0.1/1000 = 10*-4Ghz
10. Homework
    TP=1ms
    frequency in terms of GHz? TP=1sec
    frequency in terms of Khz?
11. homework
    Generate a clock of 20Mhz frequency
    Generate clock with 60% duty cycle
    Convert 25KHz clock in to Time period in us(micro seconds).
    200Mhz clock in TP in milli seconds(ms)
    TP=50ms, what is clock frequency in GHz
    Write Verilog code for 3×1 mux(4th selection case, output should hold the value)
    Write a Verilog code for 3 bit full adder.
    Also write testbench.
12. $urandom_range(90,100) => generates a random integer number between 90 to 100
    $urandom_range(90,110) => generates a random integer number between 90 to 110

SESSION#4

1. arrays

• why not use vector?

vector can only be off reg/wire data type.
integer [3:0] intvec; //NOT possible
integer intArr [3:0]; //possible

2. how arrays differs from vectors?
   • analogy
     • vector: 4 people staying in same house(same address)
     • array: 4 people staying in 4 different consecutive houses(different address)
     reg [3:0] vec;
     vec = 4’b1010; reg arr[3:0];
     arr = 4’b1010; //NOt possible
     arr[0] = 0;
     arr[1] = 1;
     arr[2] = 0;
     arr[3] = 1;
3. reg [63:0] mem[7:0];

SESSION#5

1. add two integers to return a function
   name : add
2. ALU
   name of function: alu
   inputs: operand1, operand2, operation
   operand1 : 8 bit vector
   operand2 : 8 bit vector
   operation : 4 bit
   outputs: only ‘1’
   32 bits
3. institute.grnd_floor.office_room.laptop => Hierarchical access
4. static
   123+784= 907
   489+043=532
   408+490= 898 this overrides all previous stored values.
5. 5529 = using shift and addition 55 = 32+16+4+2+1 = 110111 5529 = 55*(16+8+4+1)
   = 55<<4 + 55<<3 + 55<<2 + 55
   = 1101110000
   110111000
   11011100
   110111
6. 10%3 = 1
   10/3 = 3 => integer division
   10/3.0 = 3.333 => real division
   10.0/3.0 = 3.333 => real division
   10.0/3 = 3.333 => real division
7. a = 2**3 = 8

8.
Result is ONE bit value: 0, 1 or x
A = 6; A && B 1 && 0 -> 0 (logically false)
B = 0; A || !B 1 || 1 -> 1
C = x; C || B x || 0 => x, c && b = 0
A is logically true, B is logically false
C is logically unknown.

A = true
B = false
C = unknown
A && B = true && false = false = 0
A || B = true || false = true = 1
A || !B = true || true = true = 1
C || B = unknown || false = unknown
C || !B = unknown || true = true
x | 1 = 1

9.
module tb;
reg [9:0] a;
initial begin
a = -9;
~a

10.
Homework
a = b << c;
in above, what is operator and what are operands?
how shift operator makes multiplication easier to implement?
what is the difference between logical not and bitwise inversion?
a = -1, b = 1, c = a && b; what will be c?
a = -1, b = 1, c = a & b; what will be c?
size needs to be provided, assume integers.
a = -7, b = 11, both are integers, what is a & b?
real a; integer b; real c;
a = 3; b = 10; c = b/a; what will be value of c?
reg [5:0] a; reg [-2:-1] b; reg [5:0] c;
a= 95;
b = 69;
c = a & b; what will be c?
c = a | b; what will be c?
How unary reduction operators make vector analysis easier?
how the operator usage differs between vectors and arrays?
We have a register which is 16 bits, we want to always write [7:4] as always 4’b1111, irrespective of other bit values, how can we implement this using bitwise operators
List down various types of operators in Verilog

reg [7:0] a = -25
what is b = a >> 2;
a = 00011001
-25 = 11100111
-25>>2 = 00111001 = 57