Total lab days: 20

VERILOG LABS # WEEK1

DAY#1

  1. GVIM
    1. Install GVIM
    1. What is GVIM, how is it different from Microsoft Word, Notepad?
    1. How to open a file using GVIM?
    1. How to enable syntax in GVIM for Verilog and SV files?
      1. https://www.vim.org/scripts/script.php?script_id=1586
      1. Download verilog_systemverilog.tar.gz
      1. $HOME below will be C:/Program files/VIM (similar path)
      1. Untar the package verilog_systemverilog.tar.gz 
        Copy  verilog_systemverilog/ftdetect/verilog_systemverilog.vim to your $HOME/.vim/ftdetect directory.  
        Copy verilog_systemverilog/syntax/verilog_systemverilog.vim to your $HOME/.vim/syntax directory. 
        Copy verilog_systemverilog/indent/* to your $HOME/.vim/indent directory
    1. How to work with GVIM effectively?
      1. https://www.youtube.com/watch?v=TWBgScnFurw  (Starts from 49th min)
      1. https://www.youtube.com/watch?v=NPtLV_hqomI  (Advanced GVIM usage)
  2. GVIM Labs
    1. https://www.vlsiguru.com/unix-labs/
      1. Step#6, Step#11,12,13,14,15
  3. www.edaplayground.com
    1. https://www.youtube.com/watch?v=A1qhavaVlnw
  4. EDA Playground Labs
    1. www.edaplayground.com
    1. Make note : design.sv, testbench.sv
      1. What are those windows?
      1. What is + symbol for?
    1. Lab
      1. Develop mux2x1 Verilog code in design.sv
      1. Develop TB for mux2x1 in testbench.sv with different inputs at various times
      1. Run the same using edaplayground
      1. Now observe the waveforms
        1. How to enable waveforms in edaplayground?
  5. Verilog Basics
    1. How Verilog differs from C language?
      1. How Hardware differs from Software?
    1. What is design?
      1. What is combinational logic?
      1. What is Sequential logic?
      1. What is combinational + sequential logic?
    1. What is testbench?
      1. What is the code written in to testbench?
    1. Difference between reg and net?
      1. Where reg is used and where net is used?
    1. Design & Testbench example
      1. Implement 2X1 using Gates
      1. Write the testbench for 2X1 Mux
        1. Apply various inputs and notice the waveform
  6. Verilog labs practice (Implement design and TB for both, practice on modelsim or edaplayground.com). For all examples display the values and view the waveforms
    1. Mux2x1 using
      1. Basics questions:
        1. What is multiplexor?
        1. What are the inputs?
        1. What are the outputs?
        1. What is input and output width?
        1. Where Multiplexor is used in digital design?
      1. Implement using Gates
        1. Understand
      1. Implement using Behavioral code
      1. Implement using Data flow modelling
      1. Implement using Switch level (practice at home)
    1. Implement 4×1 Mux using 2×1 Mux
      1. Use 2×1 mux above to implement
      1. Write testbench
    1. Implement 1bit half adder, write testbench
      1. What is half adder?
      1. What are the inputs and outputs?
      1. Implement 1 bit half adder using
        1. Behavioral coding
        1. Gate level coding
        1. Data flow
      1. Write testbench for all
        1. Notice: It is same in all the above cases
    1. Implement 1 bit Full adder using 1 bit half adder above
      1. Understand usage of nets while doing interconnections
      1. Write testbench to validate this
    1. Implement 3 bit full adder using 1 bit FA above
      1. Notice usage of 3 instances of 1 bit FA
      1. Write testbench

DAY#2

Revision

  1. GVIM
  2. EDA Playground
  3. Verilog basics

Theory Questions

  1. What is difference between Verilog and c language
  2. What is difference between design and test
  3. What is difference between reg and net
  4. What are various abstraction levels in Verilog language
  5. What is difference between combinational and sequential logic
  6. Why is clock is required in sequential circuits
  7. Why we are using gvim for veriog and system Verilog code
  8. How to turn on Verilog syntax in gvim
  9. How many inputs and outputs of 2:1mux
  10. What is difference between 1-bit full adder and 1-bit half adder

LABS:  Do all Below examples using gate level coding. Write the testbench using $MONITOR to print the output

  1. Priority encoder
  2. Decoder
  3. Code for d flip-flop
  4. Implement 3 input NAND gate using 2 input NAND gate
  5. Implement AND gate using multiplexer
  6. Implement NAND gate using multiplexer
  7. Implement XOR using multiplexer
  8. Implement multiplexer using NAND gates
  9. Implementing multiplexer using NOR gates
  10. implement multiplexer using AND gate
  11. implement 3 input AND gate using 2 input NAND gate
  12. implement 3-bit substractor

DAY#3

Revision

  1. Implementing gates using multiplexer
  2. Implementing multiplexer using gates
  3. Difference between $display and $monitor
  4. How to view the wave forms?
  5. Using nets to connects gates to each other?

Theory

  1. Sequential logic
  2. What is sequential logic?
  3. What is difference between sync reset and async-reset
  4. What is synthesis
  5. What is technology library
  6. Why flip-flops are required for implementing sequential logic
  7. How many flip-flops are required to implement 4-bit up counter?
  8. Why clock is not required in combinational logic
  9. What is clock frequency
  10. What is time period
  11. If clock frequency is 100 MHZ what is the time period
  12. If time period is 2ns what is the clock frequency
  13. What is clock duty cycle and clock jitter?

LABS

  1. Implement a synchronous d-flipflop
  2. Implement latch using behavioural code
  3. Implement flip-flop using latch
  4. Implement clock with 20ns time period
  5. generate a clock of 100MHZ frequency
  6. implement 20ns time period clock with 70% duty cycle
  7. get duty cycle from the users use $value$plusargs to read the different test case
  8. Implement asynchronous d-flipflop
  9. Understand the difference between above two flip-flops
  10. What is applying reset and what is releasing reset implement the code for that
  11. Implement t flipflop using d flipflop
  12. Implement jk flip flop to d flipflop
  13. Implement sr flipflop to t flipflop
  14. implement 3 stage flip-flops.
    1. Output of one flip-flop is input to next flip-flop.

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