Total lab days: 20
VERILOG LABS # WEEK1
- Install GVIM
- What is GVIM, how is it different from Microsoft
- How to open a file using GVIM?
- How to enable syntax in GVIM for Verilog and SV
- Download verilog_systemverilog.tar.gz
- $HOME below will be C:/Program files/VIM (similar
- Untar the package verilog_systemverilog.tar.gz
to your $HOME/.vim/ftdetect directory.
to your $HOME/.vim/syntax directory.
Copy verilog_systemverilog/indent/* to your $HOME/.vim/indent
- How to work with GVIM effectively?
- https://www.youtube.com/watch?v=TWBgScnFurw (Starts from 49th min)
- https://www.youtube.com/watch?v=NPtLV_hqomI (Advanced GVIM usage)
- GVIM Labs
- Step#6, Step#11,12,13,14,15
- EDA Playground Labs
- Make note : design.sv, testbench.sv
- What are those windows?
- What is + symbol for?
- Develop mux2x1 Verilog code in design.sv
- Develop TB for mux2x1 in testbench.sv with
different inputs at various times
- Run the same using edaplayground
- Now observe the waveforms
- How to enable waveforms in edaplayground?
- Verilog Basics
- How Verilog differs from C language?
- How Hardware differs from Software?
- What is design?
- What is combinational logic?
- What is Sequential logic?
- What is combinational + sequential logic?
- What is testbench?
- What is the code written in to testbench?
- Difference between reg and net?
- Where reg is used and where net is used?
- Design & Testbench example
- Implement 2X1 using Gates
- Write the testbench for 2X1 Mux
- Apply various inputs and notice the waveform
- Verilog labs practice (Implement design and TB
for both, practice on modelsim or edaplayground.com). For all examples display
the values and view the waveforms
- Mux2x1 using
- Basics questions:
- What is multiplexor?
- What are the inputs?
- What are the outputs?
- What is input and output width?
- Where Multiplexor is used in digital design?
- Implement using Gates
- Implement using Behavioral code
- Implement using Data flow modelling
- Implement using Switch level (practice at home)
- Implement 4×1 Mux using 2×1 Mux
- Use 2×1 mux above to implement
- Write testbench
- Implement 1bit half adder, write testbench
- What is half adder?
- What are the inputs and outputs?
- Implement 1 bit half adder using
- Behavioral coding
- Gate level coding
- Data flow
- Write testbench for all
- Notice: It is same in all the above cases
- Implement 1 bit Full adder using 1 bit half
- Understand usage of nets while doing interconnections
- Write testbench to validate this
- Implement 3 bit full adder using 1 bit FA above
- Notice usage of 3 instances of 1 bit FA
- Write testbench
- EDA Playground
- Verilog basics
- What is difference between Verilog and c language
- What is difference between design and test
- What is difference between reg and net
- What are various abstraction levels in Verilog language
- What is difference between combinational and sequential
- Why is clock is required in sequential circuits
- Why we are using gvim for veriog and system Verilog
- How to turn on Verilog syntax in gvim
- How many inputs and outputs of 2:1mux
- What is difference between 1-bit full adder and
1-bit half adder
LABS: Do all Below
examples using gate level coding. Write the testbench using $MONITOR to print
- Priority encoder
- Code for d flip-flop
- Implement 3 input NAND gate using 2 input NAND gate
- Implement AND gate using multiplexer
- Implement NAND gate using multiplexer
- Implement XOR using multiplexer
- Implement multiplexer using NAND gates
- Implementing multiplexer using NOR gates
- implement multiplexer using AND gate
- implement 3 input AND gate using 2 input NAND gate
- implement 3-bit substractor
- Implementing gates using multiplexer
- Implementing multiplexer using gates
- Difference between $display and $monitor
- How to view the wave forms?
- Using nets to connects gates to each other?
- Sequential logic
- What is sequential logic?
- What is difference between sync reset and async-reset
- What is synthesis
- What is technology library
- Why flip-flops are required for implementing
- How many flip-flops are required to implement 4-bit
- Why clock is not required in combinational logic
- What is clock frequency
- What is time period
- If clock frequency is 100 MHZ what is the time
- If time period is 2ns what is the clock
- What is clock duty cycle and clock jitter?
- Implement a synchronous d-flipflop
- Implement latch using behavioural code
- Implement flip-flop using latch
- Implement clock with 20ns time period
- generate a clock of 100MHZ frequency
- implement 20ns time period clock with 70% duty
- get duty cycle from the users use
$value$plusargs to read the different test case
- Implement asynchronous d-flipflop
- Understand the difference between above two
- What is applying reset and what is releasing
reset implement the code for that
- Implement t flipflop using d flipflop
- Implement jk flip flop to d flipflop
- Implement sr flipflop to t flipflop
- implement 3 stage flip-flops.
- Output of one flip-flop is input to next