Verilog HDL Question Paper

Max Marks : 100                                                                                               Short questions : 17 x 3 = 51

Max Time : 2 hour                                                                                            Long questions : 7 x 7 = 49

Attempt all questions                                                                                    No negative marking

Short Questions

Q1. What is sensitivity list in Verilog HDL always block? What happens if you miss it?

Q2. What is the difference between a wire and a reg ? What are their default values?

Q3. What is the difference between casex, casez, case statements?

Q4. What is the difference between a latch and a flip-flop? Give four such differences?

Q5. Explain the difference between the following two verilog code lines? Do they work?

       #5 a = b;        a = #5 b;

Q6. Explain the difference between a blocking and a non blocking assignment using verilog code?

       What is the difference in their execution?

Q7. How do you model a DFF with synchronous and an asynchronous reset in verilog? Give example?

Q8. What happens if the connecting wires have length mismatch? Give example?

Q9. What is white box testing and black box testing? Which verilog modeling style models these?

Q10. What are the various modeling styles in Verilog? Give examples of each?

Q11. How can you model a latch and a flip-flop in verilog using behavioral modeling? Give example.

Q12. Given the following diagram compute the delay at which the output would appear when the inputs are x1 = 0, x2 = 1, x3 = 0 and x1 = 0, x2 = 1, x3 = 1 ? Assume delays as gate delays.

x1, x2 input to AND gate whose delay is 50ns(gate delay)

output of above AND gate is input to OR (other input is x3), OR gate delay is 75ns

Q13. Explain the differences between a function and a task?

Q14. What hardware does a conditional operator ‘?:’ models? What can you say about if – else ?

 Short Questions

Q15. What is RTL? What are the verilog modeling styles that can model RTL?

Q16. Can we write nested initial and always block? If yes give reason for the same? If no, give reason for the same? What are the other constructs with which we can model concurrent statements in Verilog?

Q17.What are the operators in verilog that model the equality/inequality with values ‘x’ and ‘z’? What other construct in Verilog allows the processing of values ‘x’ and ‘z’?

Long Questions

Q18. Given a simple and gate with two inputs a, b and an output c, write verilog code using the gate level, dataflow and behavioral modeling styles?

Q19. Write the verilog code for a clock using three different ways?

DIagram is as below:

4 back to back connected D Flipflops, last FF output is input to first FF

Q20. Given the following diagram write verilog HDL for this? What hardware does this diagram models?

Q21. Given the following verilog code, depict what hardware does it create? Give the block diagram for the same?

always @ (posedge clk or negedge reset)

begin

   if (!reset) a <= 0;

   else a <= b;

end

Q22. Write the verilog code for an 8-bit counter? Write a test-bench also?

Q23. Write the verilog code for  halfadder? Use the concept of instantiation and write the verilog code for a 4-bit ripple-carry fulladder using this halfadder?

Q24. Consider the problem of a Traffic Light Signal in whatever way you understand. Write a state machine diagram for the same and write the verilog code for this state machine?

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