Concepts to learn:

• DFF coding in Behavioural and Gate level.
• Ring counter
• Ring up-down counter
• Gray counter
• Modulo-n counter
• Johnson counter
• Why counters are required in designs? Practical applications for each type of counter
• Ring counter: counting transaction and pkts
• Gray counter: Asynchronous FIFO
• Module-n counter: Timer with specific timeout value

Each counter must be parameterizable for counter bit width. All results in below questions must be verified from Waveform. All submissions should have waveform put in word document with questions title.

1. DFF implementation
1. Implement DFF using behavioural and gate level.
1. Ports: clk, rst, d, q
1. Synchronous reset DFF
1. Asynchronous reset DFF
1. DFF Gate level implementation
• Develop testbench.
• Learn how to generate clock and reset
• Clock generation:
• Clk = 0
• Forever #5 clk =  ~clk;
• Reset generation
• Rst=1;
• @(posedge clk);
• Rst=0;
• Up Counter
• Ports
• Input: clk, rst
• Output : count
• Behavioral code
• Implemented using behavioural logic
• Gate level implementation
• Write logic truth table
1. Implement Current value using 3 bit register(since 3 bit counter)
1. Implement next value using 3 bit register (next_count[2:0])
1. Use Karnaugh map for each bit of next_count[2:0]

Ex:

Write logic for Next_count[1], Next_count[0]

Now come up with logic for next_count[2,1,0] using count

Next_count[2] <= (~count[0]&count[2]) | (count[0] & ~count[1])

Similarly come up with logic for next_count[1], next_count[0]

• Implement above logic for all the 3 bits of next_count[2:0] using Flipflop and gates
• ~  => not gate
• & => and gate
• | => or gate
• <=  indicates a Flipflop
• Understand issue if Flipflop is not used before next_count? (creates 0 delay loop, how?)
• Implement testbench to check the Up Counter behaviour
• Create Ring Counter module instance
• Generate clk(T=10ns), rst
• Write \$monitor to Check design output at each clock edge
• If reset is applied, count should be made ‘0’
• Generate scenario in initial block
• Randomly keep applying rst  and releasing rst with random delay between 100 to 200ns
• Up-down Counter
• Ports
• Input: clk, rst, up_down
• Output : count
• Behavioral code
• Implemented using behavioural logic
• Counter will act as a up counter if up_down=1
• Counter will act as a down counter if up_down=0
• Gate level implementation
• Write logic truth table
1. Implement Current value using 3 bit register & up_down(since 3 bit counter)
1. Implement next value using 3 bit register (next_count[2:0])
1. Use Karnaugh map for each bit of next_count[2:0] using count and up_down
• Implement above logic for all the 3 bits of next_count[2:0] using Flipflop and gates
• ~  => not gate
• & => and gate
• | => or gate
• <=  indicates a Flipflop
• Understand issue if Flipflop is not used before next_count? (creates 0 delay loop, how?)
• Implement testbench to check the Ring up down Counter behaviour
• Create Ring Counter module instance
• Generate clk(T=10ns), rst
• Write \$monitor to Check design output at each clock edge
• If reset is applied, count should be made ‘0’
• Generate scenario in initial block
• Randomly keep applying rst  and releasing rst with random delay between 100 to 200ns
• Randomly keep generating up_down to 0 / 1 with 50 to 100ns delay
• Gray code Counter
• Why gray code counter is required
• Required when we need only 1 bit to change in count while counter is incremented or decremented.
• In other counter there will be cases where more than 1 bit changes.
• Ex: 3’b011 => 3’b100 (all 3 bits are changing) in ring counter
• Gray counter helps avoid this.
• Ports
• Input: clk, rst
• Output : count
• Behavioural code
• Implemented using behavioural logic
• Counter will act as a up counter if up_down=1
• Counter will act as a down counter if up_down=0
• Gate level implementation
• Write logic truth table
• Implement Current value using 3 bit register
• Implement next value using 3 bit register (next_count[2:0])
• Use Karnaugh map for each bit of next_count[2:0] using count and up_down
• Implement above logic for all the 3 bits of next_count[2:0] using Flipflop and gates
• ~  => not gate
• & => and gate
• | => or gate
• <=  indicates a Flipflop
• Understand issue if Flipflop is not used before next_count? (creates 0 delay loop, how?)
• Implement testbench to check the Ring up down Counter behaviour
• Create Gray code Counter module instance
• Generate clk(T=10ns), rst
• Write \$monitor to Check design output at each clock edge
• If reset is applied, count should be made ‘0’
• Generate scenario in initial block
• Randomly keep applying rst  and releasing rst with random delay between 100 to 200ns
• Below is how waveform should like
• Module-n counter
• Module-n counter counts from 0 to n-1
• Ex: module-6 counter counts from 0..5 then repeats
• Implement this logic using both behavioural code and gate level logic derived from Karnaugh map
• Johnson counter
• Implement this logic using both behavioural code and gate level logic derived from Karnaugh map