**4×1 Multiplexor using Kmaps**- Truth table for Mux output
- Ideally we will need 64 entry truth table, but with proper understanding, we can do it in 4 entries.
- Truth table:

- i0 i1 i2 i3 s0 s1 y

- ———————-

- 0 0 i0 => this entry is y = ~s0~s1i0

- Like above total 4 entries will be there.
- All this minterms are ORed to get the final expression

- Ideally we will need 64 entry truth table, but with proper understanding, we can do it in 4 entries.

- K-Maps
- K-map is not required

- Boolean expression
- Show the final expression.

- Implement Boolean expression using Verilog logic gates
- Inbuilt logic gates

- Module ports?
- How many inputs?

- How many outputs?
- Outputs declared as reg or wire.

- Boolean expression: y= ~s0~s1i0 + s0~s1i1 + ~s0s1i2 + s0s1i3
- OR of 4 AND gates.

- How to implement AND gate in Verilog

- Write a testbench
- Use $random with input variable concatenation to generate random inputs
- {i0, i1….} = $random;

- What does $random do?
- Generates a 32 bit random number

- What is { } does?

- Repeat this for 20 times
- Why we need do give #1 delay inside repeat?

- Many students declaring n1, n2, n3, n4 in testbench also.
- Which should not be done

- Only Design inputs and outputs should be copied to testbench file, not the design internal signals.

- Use $random with input variable concatenation to generate random inputs

- $monitor to display and check the outputs
- Write $monitor with $time printed

- Check how many times display happens

- Why some timesteps are not displayed.

- Understand how $display differs from $monitor

- Also add signals to the waveform and check the behaviour.

- Truth table for Mux output
- Implement 4×1 Mux using behavioural code
- Always

- Mux behaviour implemented using if else statements
- Same can be done using case statement also.

- Implement 4×1 Mux using continuous assignments, i.e. Data flow model.
- Assign Y = S1 ? (S0 ? i3 : i2) : (S0 ? i1 : i0);
- Do not code assign inside always

- Assign Y = S1 ? (S0 ? i3 : i2) : (S0 ? i1 : i0);
- Implement 8×1 Mux using 4×1 Mux?
- Come up with 8×1 Mux diagram using 4×1 mux only (don’t use 2×1 mux)

- Instantiate 4x1mux to create 8×1 mux design Verilog code.

- This concept is called as Hierarchical modelling.
- Using smaller modules, creating bigger modules.

- Module mux8x1
- How many ports?
- Inputs: 11

- Outputs: 1

- There won’t be any logic coding. It is all about instantiating 4×1 mux 3 times, connecting its ports.

- How many ports?

- How to instantiate first 4×1 Mux in the design
- Mux4x1 u1(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .s0(s0), .s1(s1), .y(n1));
- Connection by name

- Mux4x1 u1(i4, i5, i6, i7, s0, s1, n1);
- Connection by position

- Ports order mux4x1 should be in same order as above.

- Mux4x1 u1(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .s0(s0), .s1(s1), .y(n1));

- Scalar and vector declaration
- Declare a net type scalar of name ‘valid’

- Declare a reg type scalar of addr

- Declare a 33-bit reg vector named wdata

- Declare a 64-bit net vector named rdata

- Declare an 8-bit vector of name ‘write_data’ which is output of and gate.

- vector to vector assignment
- Both same size
- Reg [3:-2] a;

- Reg [7:2] b;

- a = b
- what position of b is copied to what position of a?

- LHS bigger than RHS
- Reg [3:-5] a;

- Reg [7:2] b;

- a = b
- what position of b is copied to what position of a?

- LHS smaller than RHS
- Reg [3:-2] a;

- Reg [7:0] b;

- a = b
- what position of b is copied to what position of a?

- Both same size
- Radix conversion
- Represent Decimal 743 as 16-bit variable in all radix
- Octal, Hexa, Decimal, Binary

- Convert 16’h7654 to all other radix formats.

- Convert 16’o45632 to hexa decimal format.

- Represent Decimal -743 (minus 743) as 16-bit variable in all radix
- Octal, Hexa, Decimal, Binary

- Represent Decimal 743 as 16-bit variable in all radix

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