VLSI Guru verilog-assignment-2

4×1 Multiplexor using Kmaps
1. Truth table for Mux output
  1. Ideally we will need 64 entry truth table, but with proper understanding, we can do it in 4 entries.
    1. Truth table:
    1. i0 i1 i2 i3 s0 s1 y
    1. ———————-
    1. 0 0 i0 => this entry is y = ~s0~s1i0
    1. Like above total 4 entries will be there.
      1. All this minterms are ORed to get the final expression
1. K-Maps
  1. K-map is not required
  1. Boolean expression
    1. Show the final expression.
1. Implement Boolean expression using Verilog logic gates
  1. Inbuilt logic gates
  1. Module ports?
    1. How many inputs?
    1. How many outputs?
      1. Outputs declared as reg or wire.
  1. Boolean expression: y= ~s0~s1i0 + s0~s1i1 + ~s0s1i2 + s0s1i3
    1. OR of 4 AND gates.
    1. How to implement AND gate in Verilog
1. Write a testbench
  1. Use $random with input variable concatenation to generate random inputs
    1. {i0, i1….} = $random;
    1. What does $random do?
      1. Generates a 32 bit random number
    1. What is { } does?
  1. Repeat this for 20 times
    1. Why we need do give #1 delay inside repeat?
  1. Many students declaring n1, n2, n3, n4 in testbench also.
    1. Which should not be done
    1. Only Design inputs and outputs should be copied to testbench file, not the design internal signals.
1. $monitor to display and check the outputs
  1. Write $monitor with $time printed
  1. Check how many times display happens
  1. Why some timesteps are not displayed.
  1. Understand how $display differs from $monitor
1. Also add signals to the waveform and check the behaviour.
Implement 4×1 Mux using behavioural code
1. Always
1. Mux behaviour implemented using if else statements
  1. Same can be done using case statement also.
Implement 4×1 Mux using continuous assignments, i.e. Data flow model.
1. Assign Y = S1 ? (S0 ? i3 : i2) : (S0 ? i1 : i0);
  1. Do not code assign inside always
Implement 8×1 Mux using 4×1 Mux?
1. Come up with 8×1 Mux diagram using 4×1 mux only (don’t use 2×1 mux)
1. Instantiate 4x1mux to create 8×1 mux design Verilog code.
1. This concept is called as Hierarchical modelling.
  1. Using smaller modules, creating bigger modules.
1. Module mux8x1
  1. How many ports?
    1. Inputs: 11
    1. Outputs: 1
  1. There won’t be any logic coding. It is all about instantiating 4×1 mux 3 times, connecting its ports.
1. How to instantiate first 4×1 Mux in the design
  1. Mux4x1 u1(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .s0(s0), .s1(s1), .y(n1));
    1. Connection by name
  1. Mux4x1 u1(i4, i5, i6, i7, s0, s1, n1);
    1. Connection by position
    1. Ports order mux4x1 should be in same order as above.
Scalar and vector declaration
1. Declare a net type scalar of name ‘valid’
1. Declare a reg type scalar of addr
1. Declare a 33-bit reg vector named wdata
1. Declare a 64-bit net vector named rdata
1. Declare an 8-bit vector of name ‘write_data’ which is output of and gate.
vector to vector assignment
1. Both same size
  1. Reg [3:-2] a;
  1. Reg [7:2] b;
  1. a = b
    1. what position of b is copied to what position of a?
1. LHS bigger than RHS
  1. Reg [3:-5] a;
  1. Reg [7:2] b;
  1. a = b
    1. what position of b is copied to what position of a?
1. LHS smaller than RHS
  1. Reg [3:-2] a;
  1. Reg [7:0] b;
  1. a = b
    1. what position of b is copied to what position of a?
Radix conversion
1. Represent Decimal 743 as 16-bit variable in all radix
  1. Octal, Hexa, Decimal, Binary
1. Convert 16’h7654 to all other radix formats.
1. Convert 16’o45632 to hexa decimal format.
1. Represent Decimal -743 (minus 743) as 16-bit variable in all radix
  1. Octal, Hexa, Decimal, Binary