Ports order mux4x1 should be in same order as above.
Scalar and vector declaration
Declare a net type scalar of name ‘valid’
Declare a reg type scalar of addr
Declare a 33-bit reg vector named wdata
Declare a 64-bit net vector named rdata
Declare an 8-bit vector of name ‘write_data’ which is output of and gate.
vector to vector assignment
Both same size
Reg [3:-2] a;
Reg [7:2] b;
a = b
what position of b is copied to what position of a?
LHS bigger than RHS
Reg [3:-5] a;
Reg [7:2] b;
a = b
what position of b is copied to what position of a?
LHS smaller than RHS
Reg [3:-2] a;
Reg [7:0] b;
a = b
what position of b is copied to what position of a?
Radix conversion
Represent Decimal 743 as 16-bit variable in all radix
Octal, Hexa, Decimal, Binary
Convert 16’h7654 to all other radix formats.
Convert 16’o45632 to hexa decimal format.
Represent Decimal -743 (minus 743) as 16-bit variable in all radix
Octal, Hexa, Decimal, Binary
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