Concepts to learn:

There will not be clk,rst in below examples since it is combinational logic.

Common concepts:

Design coding:

Testbench coding:


  1. How hardware differs from software?
  2. How Verilog implements
    1. Concept of time
    1. Concept of structure
    1. Concept of concurrent process
    1. Concept of states
  3. How Verilog language differs from C language?
  4. Why Verilog is called as Hardware description language, not a programming language?
  5. What does EDA stand for?
  6. How EDA tools make the whole VLSI design process easier?
  7. Half Adder
    1. Ports
      1. Input: a, b (8 bit vectors)
      1. Output: s, co
    1. Implement half adder logic using assign
    1. Implement testbench to check the half adder behaviour
      1. Testbench file name: tb_ha.v
        1. Use :spl to create a new file tb_ha.v
      1. Include ha.v in tb_ha.v
      1. Declare all design inputs as reg
        1. Copy the same line as in design file, use ‘cw’ command to change input to reg.
          1. Use yy, y1 commands to copy lines from design file and use ‘p’ to paste in tb file.
      1. To switch between each file, use ‘Ctrl+w’, followed by up or down arrow
      1. Create half adder module instance
        1. Use ctlr+w and arrow to move cursor to ha.v file
        1. Go to design module definition line(line number 1)
          1. Use up or down arrow to move the cursor
        1. yy
        1. ctrl+w, arrow move to tb_ha.v
        1. ‘p’ to paste that line in tb_ha.v
          1. Go to the line below which we want to paste module definition
        1. Remove module
          1. Keep cursor on m of the module
          1. dw
      1. Drive a, b with random value
      1. Use $monitor to monitor a, b, s and co
    1. Implement half adder logic in always block
      1. Always @(a or b)
        1. Anytime a or b changes, half adder should work
    1. Implement half adder using logic gates
      1. Truth table, K-maps, Boolean expression, circuit, coding
      1. For a 8 bit input vectors, it’s quite complex
      1. DO it only using 1 bit half adder and tb also for 1 bit ha.
  8. Full adder
    1. Use half adder coded above to implement full adder
      1. Search how to implement full adder using half adder in google.
      1. Use ha_gate.v, 1 bit Half adder to do this.
      1. If this works, see how 8 bit FA can also be implemented.
    1. Write test bench to check design behaviour
  9. Multiplexer (8 to 1 mux)
    1. Implement 8 to 1 mux
    1. Write testbench to check design behaviour
  10. Encoder, decoder and priority encoder
    1. Implement above designs
    1. Write testbench to check design behaviour
  11. Encoder, decoder and priority encoder implementation using multiplexer
    1. Implement above designs using multiplexer
    1. Write testbench to check design behaviour
  12. Implementing various gates using multiplexer
    1. Implement AND, OR, NAND, NOR, XOR, XNOR using multiplexer
  13. 4×1 Multiplexor using K-Maps
    1. Implement truth table
    1. Use K-maps to come up with Boolean expression for 4×1 Multiplexor
    1. Write the Verilog code using above expression
    1. Develop testbench and run the simulation.
  14. Parameterizable full Adder (once parameter concept is taught)
    1. Same as above except module being parameterizable for width of input and output that half adder supports

10. Implementing a simple gate level design using gate level modeling

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