Ports order mux4x1 should be in same order as above
Multiplexer (8 to 1 mux)
Implement 8 to 1 mux
Write testbench to check design behaviour
Encoder, decoder and priority encoder
Implement above designs
Write testbench to check design behaviour
Encoder, decoder and priority encoder implementation using multiplexer
Implement above designs using multiplexer
Write testbench to check design behaviour
Implementing various gates using multiplexer
Implement AND, OR, NAND, NOR, XOR, XNOR using multiplexer
4×1 Multiplexor using Boolean expression
Write the Verilog code using above expression
Develop testbench and run the simulation.
Implement 1-bit half subtractor
Using above implement 1 bit full subtractor
Using above implement 3 bit full subtractor
Implement 8×1 mux using
2 – 4×1 Mux
1 – 2×1 Mux
Implement 1 bit comparator
Behavioral
Data flow
Structural
Implement 2 bit comparator
Behavioral
Data flow
Structural
Using 1 bit comparator
Implement multi bit comparator
Behavioral
Data flow
Structural
THEORY QUESTIONS
How hardware differs from software?
How Verilog implements
Concept of time
Concept of structure
Concept of concurrent process
Concept of states
How Verilog language differs from C language?
Why Verilog is called as Hardware description language, not a programming language?
What does EDA stand for?
How EDA tools make the whole VLSI design process easier?
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