/Concepts:

Question:

  1. Declare dual port ram will below ports
    1. Clk, rst, addr_wr, addr_rd, wr, rd, data_wr, data_rd
    1. Declare a memory using array, array size based on address port width
    1. When rst = 1, reset memory contents
    1. When wr = 1, write data in to memory
    1. When rd = 1, read data from memory
  2. TB Coding
    1. Instantiate memory
    1. Generate clk, rst(2 clocks)
    1. Write different cases
      1. Write all 256 locations, read back all of them
      1. Do parallel write/read
      1. DO rand parallel write/read’s
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