1. what is UVM?

$display(“ERROR : tx failed”);

`uvm_error(“id”, “tx failed”);

  1. what are the advantages of UVM?
  1. what is factory in UVM?

class ahb_driver extends uvm_driver#(ahb_tx);
`uvm_component_utils(ahb_driver) //ahb_driver is registered in to factory

  1. How to we create a component instance using factory defintion?
    ahb_driver drv;
    drv = ahb_driver::type_id::create(“drv”, this);
  2. How to we create a component instance using SV file definition?
    ahb_driver drv;
    drv = new(“drv”, this);
  3. Benifits of factory in UVM?
  1. What is factory registration?
  1. What is the difference between uvm_component and uvm_object?
  1. What are the benefits of component/object factory registration?
  1. what is objections in UVM?
  1. what is the typical UVM TB structure?
    Testbench top most module -> root -> testcase instance -> top_env instance -> sub_env, scoreboard, register model ->(sub_env) -> master agents &/or slave_agents -> driver, Sequencer, monitor, coverage
  2. what is uvm_root? significance in UVM TB?
  1. what are the various UVM phases?
  1. Why UVM build_phase is top-down?
  1. what parent & children in UVM?
    for test : parent: uvm_root, children: env
    for env : parent: test(uvm_test_top), children: sub_env’s
    for sub_env : parent: env, children: agent’s
  2. how UVM enviroenment is started?
    top most module:
    initial begin
    run_test(“ahb_10_tx_test”); //we are starting ahb_10_tx_test
    //it will automatically start running all UVM phases one by one.
  3. which is the only phase where objections can be raised and dropped?
  1. what are the different ways to specify which testcase we want to run?
  1. what is difference between uvm_seqeunce and uvm_seqeunce_item?
  1. what is TLM in UVM?
    TLM stands for Transaction Level Modeling, it is a set of base classes with pre-implmeneted mehtods used to connect various TB components.
  2. what is the difference between seq_item_port and analysis_port?
    seq_item_port is used between driver and sequencer, where communicaton is only 1 to 1
    analysis_port is used for 1 to many connections, like monitor to coverage/ckr/ref_model etc
  3. what is the difference between push model and pull model in TLM?
    push model: producer acts as a master of the communication
    pull model: consumer acts as a master of the communication
  4. how TLM differs from mailbox in SV?
  1. what are the various types of testcases developed in verification?

UVM Interview preparation : 18/JAN/2020

  1. Siliconch : 6L/A
  2. Atria logic :


  1. why connect_phase is bottom up?
    • this is UVM methodology has been defined
    • connect_phase being a function, it gets over in 0 time
  2. RAL

RAL has 5 sets of value for each register:
– value
– dut_value : Value of the register inside the DUT
– m_reset_value : value of the register at reset
– m_desired_value : value of the register, what user thinks it should be
– m_mirrored_value : value that is being mirrored from DUT to TB

INTR Status register:
– keeps track of interrupt status
intr_sts_reg = 32’h1234_5600;
intr_sts_reg.m_desired_value = 32’hABCD_EFGH;
reg_block.intr_sts_reg.mirror(status, UVM_CHECK);
– dut value will be mirrored in to m_mirrored_value
since we are using UVM_CHECK, it will also do the check(comparison of m_mirrored_value with m_desired_value)

Backdoor access:

  1. Register layer has 2 types of access
    • front door
      o write, read, update, mirror
    • back door
      o peek, poke
      poke: write in to the register using register hierarchy path
      peek: read from the register using register hierarchy path

– during the register model definition, we would have specified the hierarchy of CSR register

  1. register test cases
    • 4 combinations
  2. how to end simulation without using $finish and withotut dropping objection?
    vsim work.top +UVM_TIMEOUT=1000
    default UVM_TIMEOUT value is 9200sec
  3. vsim work.top +UVM_OBJECTION_TRACE
  1. where do we use export in TLM1.0?
    • export is used where the component is not supposed to consume the transaction, it is supposed to forward the incoming transaction to other port, final consumer is someother block
  2. lock, grab
    lock: append
    grab: prepend


Order of execution will be:
SEQ1 -> SEQ4 -> SEQ2 -> SEQ3

  1. seq1.start(agent.sqr);
    sequence1.kill() or sequencer.stop_sequences()
  2. difference between p_sequencer and m_sequencer?
    • both these keywords are used from a sequence perspective
    • p_sequencer refers to teh virtual seqeuncer on which curretn sequence should be run.
      • m_sequencer refers to master seqeuncer for given non-virtual seqeuence. ex: seq3, if seq3 is of type axi_10_tx_seq, m_sequencer will be axi_sqr
        • p_sequencer comes in to place since we define `uvm_declare_p_sequencer inside the seqeunce code
  3. difference between config_db and resource_db?
    • config_db is a extended class of uvm_resoruce_db
    • they differentiate based on how the DB register variables are accessed.
      • config_db variables are accessed based on the compoennt hiearchy
      • resource_db variables are accessed based on the SCOPE and KEY indepdendet of hiearchy
  4. is it possibel to set a vairbale in lower heirarhcy in to config_db and get in upper heirarhcy?
  5. TLM and mailbox differences?
    – TLM provides seemless connection
    o we don;t need to pass the TLM object handle to any otehr component
    – TLM provides bidirection communication models
    seq_item_port.get_next_item(req); //item from sqr -> driver
    seq_item_port.item_done(rsp); //item from driver -> sqr
    – TLM comes with in built methods for diffeent TB requirements
    – only provides one-direction communication model
    – maiobox will not be suitable for broadcast model
    – mailbox requires user to pass the mailbox handle to btoh producer adn consumer
  6. uvm_root?
  7. difference between uvm_report_object and uvm_report_handler?
  1. drain_time?
    • additional time for which simulation should run once all raised objectons are dropped
  2. what are different steps in uvm_do?
    • it is implement in 7 stpes
      • create
      • pre_do
      • mid_do
      • randomize
      • post_do
      • wait_for_grant
      • item_done
  3. what is run_test in UVM?
    • run_test is global method, which will create the instance of uvm_root as top. It will inturn call the top.run_test method, which will essentially start the uvm_root functionality.
  4. uvm_resource_db, what is difference b/w read-by_name and read_by_type?
  1. when do we prefer resoruce_db over config_db?
  1. difference b/w uvm_info, uvm_report_info?
    • uvm_info is a macro, which inturn calls uvm_report_info.
      o uvm_info on top of uvm_report_info, it automatically prints the file name and line number.
  2. what is type_id?
    • type_id is the factory definition of the component/object class. it is of type uvm_object_registry or uvm_component_registry with current class parameterized.
      ahb_driver::type_id is the ahb_driver factoruy definition
      ahb_monitor::type_id is the ahb_monitor factoruy definition
  3. testbench?
    • platform build around DUT, so that inputs can be applied as per current testcase and output can checked for testcase reqiroments.
  4. factory?
    • utility class which holds all the compoennt and object defiitions. This is globally accessible so that these defiitions can be changed as per test requirments.
  5. what is override in UVM? what are different types of overrides?
    • override is a concept which enables user to change the factory definition of a given component/object without changing the file definition of the same. This allows user to have a component/object definition for current testcase requirements. Two types of overrides, 1. type override 2. inst override
    • type override will change the definition of the component/object for all the instances of the component or object
    • inst override will change the definition of the component/object only for specific instances or heirarchies of the component or object
  6. what is difference b/w create and new?
  1. why do we pass uvm_phase vairbale with UVM phase methods?
    • uvm_phase phase is singleton class which has handle created in uvm_root. passing this variable makes sure that all raise and drop objections can be tracked in uvm_root.
  2. what is benefit of parent and name in new defnition?
    • these will be useful in coming up with complete TB hierarchy and also helps in assigning unqiue instance(full) names to each of the components.
  3. uvm_report_catcher?
    • when user implements a error testcase, test is supposed to fail with uvm_error reporting. But I still want this messages to be changed to lower severity so that testcase will pass. But uvm_report_catcher will report what severity changes have been done and which messages have been changed.
    • uvm_report_catcher will work w.r.t testcases.
  4. every uvm_component based class have set_action method, using which we can change the specific message action levels.
  5. uvm_component cmp;
    cmp = drv;
    cmp.buil_phase will still refer to drv method.
  6. explain sqr-drv communication model?
  1. what is diffeence b/w uvm_tlm_fifo and uvm_analysis_fifo?
  2. benefits of methodology?
    • set of very well defined guildelines on how to do every asepct of verification. methodology also provides base classes and macro to do these implementation with minimal effort.
    • TB becoems reusable and easy to update for new requiremnts
    • easy for new engineer to ramp up.
  3. concept of TLM?
    TLM implements the communicaiton between 2 components, one producing and other consuming. One fo these compoennts calls a method and otehr compoennt implement this method, though this mehtod call tx gets passed from one compoennt to anotehr.
  4. uvm_heartbeat


  1. What is clocking block? how it helps avoid possible race conditions between design and TB?
    Clocking block is a langauge consturct defined as part of interfaces for aceiving synchoronization between design and TBs.
    It uses cocnept of input skew and output skew for achievie the synchoronization.
    output skew indicates how much time after +edge of the clock, design inputs should be driven(BFM will drive these inputs). Since BFM is driving these signals, this skew is called as output skew. This concept makes sure that design gets most stable input value.
    INput skew indicates how much time before +edge of the clock, design output should be sampled(BFM will sample these). Since BFM is sampling(collecting) these signals, this skew is called as input skew. This concept makes sure that BFM(TB) gets most stable values of design output.
    hence clocking blocks makes sure the stable values of design inputs and outptus are driven/sampled by using outptu and input skews.

2 kinds of interfaces:
– synchornous
o all signal driving and sampling has to be synchornous w.r.t to some signal(generally that some signal is called as clock)
o two types of signals at every interface
o input : need to be driven in to the design
o inputs are driven by BFM => for BFM signals are output, when is the best time to drive
o when is the write time to drive?
this delay after which we want to drive the design inputs is called as output skew.
clocking master_cb@(posedge clk);
output #2 addr; //2 units after #edge of clock address should be driven
output #3 wdata; //2 units after #edge of clock address should be driven
– best time drive the design inputs is just after the +edge of the clock.
o output: need to be sampled by teh TB
BFM needs to sample these outputs
when it best time to sample?
amount of time before the +edge of the clock when design outputs should be sampled, is called as input skew.
o skew’s are being discussed here from BFM perspective.
o input skew: how mucj time before +edge of clock to sampel design outputs
o output skew: how mucj time after +edge of clock to drive design inputs
o CLOCKING BLOCK: drive design inputs in such a way that it gets most stable values. Sample design outputs in such a way that we get most stable outputs from the design.
– asynchornous
o there is no clock on these interfaces.
o Driving/sampling will happen purely based on delays.

  1. What is the difference between parameter and macro? which one is preferred?
  1. what is the signifniance of uvm_root in UVM based TBs?
  1. what is starting_phase in UVM?
  1. what is difference between aligned and unaligned transfers?
  1. what is TLM? what are the different connection types in TLM1.0?
  1. what are the types of overrides in UVM? how override helps in UVM TB?
  1. what is the difference between new and create?
  1. explain the communicaiton between driver and seqeuncer?
  1. what are the benefits of factory registration?

11. what are the different steps in uvm_do macro?

Course Registration