Below is the quick overview of course. Please make sure you are added to whatsapp group to get all course notifications.

Please send mail to contact@vlsiguru.com for any clarifications.

  1. Course duration and schedule
    1. Duration: 8 weeks
  2. Course Checklist : Please mail to contact@vlsiguru.com for any support you need with below checklist
    1. Added to Whatsapp group
    2. UVM Course material shared from Google drive
    3. Online students: Got EDA Playground Login, Classroom students: UNIX login to access Questasim on servers
    4. Course assignment links and timelines to submit
  3. Course material
    1. Shared on GoogleDrive
      1. Labs
      2. UVM Reference Manual
    2. GVIM, Questasim and EDA-PLAYGROUND videos
      1. Using GVIM Effectively
      2. Using Questasim to run UVM based TB
      3. Using EDA Playground to run UVM based TB
      4. Enable SV Syntax in GVIM
    3. Assignments  (send solutions in doc format to submit.vlsiguru@gmail.com)
      1. uvm-assignment-1 : Setting up UVM Template TB environment
      2. uvm-assignment-2 : Objections, Phases
      3. uvm-assignment-3 : Reporting classes, Severity, verbosity
      4. uvm-assignment-4 : Factory
      5. uvm-assignment-5 : TLM 1.0
      6. uvm-assignment-6 : Config_db & Resource_db
      7. uvm-assignment-7 : Sequence Library
      8. uvm-assignment-8 : Virtual Sequencer & virtual sequence
      9. uvm-assignment-9 : Policy Classes
      10. uvm-assignment-10 : Monitor, Coverage and Scoreboard implementation and connections
      11. uvm-assignment-11 : Driver – Sequencer communication model
      12. uvm-assignment-12 : UVM Command Line processor
      13. uvm-assignment-13 : Synchronization Classes: Event, Barrier
      14. NEED TO UPDATE
      15. uvm-assignment-15 : AHB Protocol, AHB Interview questions
      16. uvm-assignment-16 : AHB UVC and AHB Interconnect TB development

Course Registration