- List down various features of
USB core
- Draw the USB core architecture
- Draw the USB core testbench
architecture
- Write down which interfaces of
USB core are master interfaces and which are slave interfaces
- List down various functionality
handled by each interface
- Ex: UTMI interface handles
speed negotiation, enumeration
- Come up with verification plan
- List down various scenarios in
USB core verification
- FS, All bulk transfers
- List down various test cases
and write the test plan, with following columns
- SNO, Feature name, scenario
targeted, test name, test description, test status, debug comments
- Develop the template
environment
- Develop the sanity testcases
- List down various sequences
that need to be developed at UTMI interface
- List down various sequences that
need to be developed at Wishbone interface(in interview always say AHB, not WB)
- Model the SRAM behavior using
Verilog code
- Draw the timing diagram for
Write/read at SRAM interface
- Write the detailed steps
followed in coding various testbench components.
- Top-down or bottom-up?
- What do code in top.sv?
- Do we need virtual sequencer?
- How many sequence library’s are
required?