1. List down various features of USB core
  2. Draw the USB core architecture
  3. Draw the USB core testbench architecture
  4. Write down which interfaces of USB core are master interfaces and which are slave interfaces
  5. List down various functionality handled by each interface
    1. Ex: UTMI interface handles speed negotiation, enumeration
  6. Come up with verification plan
  7. List down various scenarios in USB core verification
    1. FS, All bulk transfers
  8. List down various test cases and write the test plan, with following columns
    1. SNO, Feature name, scenario targeted, test name, test description, test status, debug comments
  9. Develop the template environment
  10. Develop the sanity testcases
  11. List down various sequences that need to be developed at UTMI interface
  12. List down various sequences that need to be developed at Wishbone interface(in interview always say AHB, not WB)
  13. Model the SRAM behavior using Verilog code
  14. Draw the timing diagram for Write/read at SRAM interface
  15. Write the detailed steps followed in coding various testbench components.
    1. Top-down or bottom-up?
    1. What do code in top.sv?
    1. Do we need virtual sequencer?
    1. How many sequence library’s are required?
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