Explain how various sub blocks
interface with each other
Explain what is the role of
buffer in USB core functionality
Explain the various steps in
USB device bring up in detail
Device detection
Speed negotiation
Register programming
Enumeration
Data transfers
Suspend, resume
Explain in detail various steps
in USB Frame transfer starting from Frame generation, Frame decoding, Buffer
storage, function controller communication, DMA transfers, etc
Explain for Control transfers
Explain for OUT transfers
Explain for IN transfers
Explain Interrupt generation
concept in USB
Who generates interrupt
Who services the interrupt
List down various reasons(at
least 10) why interrupt will be generated
Explain how multiple EP’s help
improve the USB core through put
Explain the role of Internal
DMA engine in USB core
Explain the role of Memory
Arbiter in USB core
Explain the need for 2 buffers
for each EP
What will be the limitation if
we have only one buffer per End point
Explain the design
configuration specific to EP’s
What is the Function Address
register in USB core?
Write down various fields in EP
register
Write the significance of each
field
Explain the significance of
Interrupt status register and interrupt mask register
What is the role of Mask
register
Why all the fields in interrupt
status register are RO or ROC? Why they are not Write fields?
Why we need interrupt register
for each endpoint? Why can’t we have a global register for all?
Explain various steps that goes
in to interrupt handling
Explain various reasons why USB
core enters in to suspend mode and how does it resume using flow diagram
Draw the timing diagram for
transfers at UTMI interface and AHB interface.
How does Function controller
keeps track of Buffer address
How does function controller
exactly know which address of SRAM it should read/write
Explain various stages that
goes in control transfers?
Explain significance of SETUP
Stage, Data stage and Status stage
What happens if buffer gets
full any time during transfers
What all types of packet checks
happen in USB core
PID check
CRC check
How USB core handles various
error conditions
What happens if device is
disconnected when transfers are in progress
How USB controller is different
from USB core
Draw the detailed architecture
diagram of USB core with various ports, their directions, sizes at each
interface.
Write the maximum sizes for
various transfer types in different speeds
Explain why Handshake packet is
not there in Isochronous transfers
Draw the state machine for
USB20 core operation
States: Detection, enumeration,
etc (refer to UTMI doc)
How to enable or disable EP’s
in the design(specific to current project)
How Function controller
transfers are identified to be either targeting Buffer memory or USB core
registers?
Hint: wb_addr[17]
List down various design
Verilog files in USB core
Come up with design
architecture diagram by referring to Verilog files(top most: usbf_top.v)
Come up with detailed directory
structure for Testbench environment
USB20_Project -> Design
-> RTL
Verif -> TOP, WB, UTMI, SIM
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