1. Draw the USB core design architecture
    1. List down various interface in USB core
    1. List down various design sub blocks in USB core
    1. List down various registers(total: 70) in USB
    1. Explain how various sub blocks interface with each other
    1. Explain what is the role of buffer in USB core functionality
  2. Explain the various steps in USB device bring up in detail
    1. Device detection
    1. Speed negotiation
    1. Register programming
    1. Enumeration
    1. Data transfers
    1. Suspend, resume
  3. Explain in detail various steps in USB Frame transfer starting from Frame generation, Frame decoding, Buffer storage, function controller communication, DMA transfers, etc
    1. Explain for Control transfers
    1. Explain for OUT transfers
    1. Explain for IN transfers
  4. Explain Interrupt generation concept in USB
    1. Who generates interrupt
    1. Who services the interrupt
    1. List down various reasons(at least 10) why interrupt will be generated
  5. Explain how multiple EP’s help improve the USB core through put
  6. Explain the role of Internal DMA engine in USB core
  7. Explain the role of Memory Arbiter in USB core
  8. Explain the need for 2 buffers for each EP
    1. What will be the limitation if we have only one buffer per End point
    1. Explain the design configuration specific to EP’s
  9. What is the Function Address register in USB core?
  10. Write down various fields in EP register
    1. Write the significance of each field
  11. Explain the significance of Interrupt status register and interrupt mask register
    1. What is the role of Mask register
    1. Why all the fields in interrupt status register are RO or ROC? Why they are not Write fields?
    1. Why we need interrupt register for each endpoint? Why can’t we have a global register for all?
  12. Explain various steps that goes in to interrupt handling
  13. Explain various reasons why USB core enters in to suspend mode and how does it resume using flow diagram
  14. Draw the timing diagram for transfers at UTMI interface and AHB interface.
  15. How does Function controller keeps track of Buffer address
    1. How does function controller exactly know which address of SRAM it should read/write
  16. Explain various stages that goes in control transfers?
    1. Explain significance of SETUP Stage, Data stage and Status stage
  17. What happens if buffer gets full any time during transfers
  18. What all types of packet checks happen in USB core
    1. PID check
    1. CRC check
  19. How USB core handles various error conditions
  20. What happens if device is disconnected when transfers are in progress
  21. How USB controller is different from USB core
  22. Draw the detailed architecture diagram of USB core with various ports, their directions, sizes at each interface.
  23. Write the maximum sizes for various transfer types in different speeds
  24. Explain why Handshake packet is not there in Isochronous transfers
  25. Draw the state machine for USB20 core operation
    1. States: Detection, enumeration, etc (refer to UTMI doc)
  26. How to enable or disable EP’s in the design(specific to current project)
  27. How Function controller transfers are identified to be either targeting Buffer memory or USB core registers?
    1. Hint: wb_addr[17]
  28. List down various design Verilog files in USB core
    1. Come up with design architecture diagram by referring to Verilog files(top most: usbf_top.v)
  29. Come up with detailed directory structure for Testbench environment
    1. USB20_Project -> Design -> RTL
      1. Verif -> TOP, WB, UTMI, SIM
Course Registration