USB20 & USB30 Training

mention of USB, PCIe, DDR in resume opens up quite of few job opportunities..that is the importance of these protocols in current SoCs..

All high speed protocols like USB3, PCIe, SATA, UFS, etc are all based on OSI architecture. Course focus on teaching all the required concepts of different layers in USB. Course also cover design & testbench implmentation for Protocol, link and physical layers of USB.

  • USB Protocol, Link, Physical layers
  • Design implementation for all layers
  • Testbench component coding for all layers
  • Course USB30 Protocol Training
    Duration 5 weeks
    Next Batch Adhoc
    Registration 24/Feb
    Schedule Both Saturday & Sunday(11AM – 2:30PM India time)
    New batch starts every 12 weeks
    Fee INR 8200 (all inclusive)
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 20
    Trainer 12+ Years exp in RTL design & Functional verification


What are the Course Prerequisites?

  • Exposure to standard bus protocols
  • Exposure to Testbench component coding using SystemVerilog

What if I miss few sessions during course?

    • Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

USB20 & USB30 specification
USB quick reference manual
USB controller design & verification code

Trainer Profile

  • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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