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AMBA(AXI, AHB, and APB)

AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols.


Bestseller

  

4.6 Star (125 rating)

525 (Student Enrolled)

Created by

Experienced Trainer


Course Overview

AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.

AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.

Introduction to on-chip protocols

  • Protocol overview
  • AXI revisions
  • AXI based system architecture

Signal descriptions

  • Global signals
  • Write address channel signals
  • Write data channel signals
  • Write response channel signals
  • Read address channel signals
  • Read data channel signals
  • Low power interface signals

Signal Interface requirements

  • Basic write and read transactions
  • Relationship between channels
  • Transaction structure

Transaction attributes

  • Transaction types and attributes
  • AXI3 memory attribute signalling
  • AXI4 changes to memory attribute signalling
  • Memory types
  • Mismatched memory attributes
  • Transaction buffering
  • Access permissions

Multiple transactions

  • AXI transaction identifiers
  • Transaction ID
  • Transaction ordering

AXI4 Ordering model

  • Definition of ordering model
  • Master ordering
  • Interconnect ordering
  • Slave ordering
  • Response before final destination

Atomic accesses

  • Single-copy atomicity size
  • Exclusive accesses
  • Locked accesses
  • Atomic access signaling

AXI4 additional signaling

  • QoS signaling
  • Multiple region signaling
  • User-defined signaling

Low-power interface

  • Low power interface signals
  • Low power clock control

Default signaling and Interoperability

  • Interoperability principles
  • Major Interface categories
  • Default signal values
  • VIP architecture
  • VIP components
  • VIP types
    • Master, Slave
    • Active, Passive
  • VIP test scenario listing down
  • VIP component coding
    • Driver, Generator, Monitor, Coverage, Environment
    • Interface, transaction, Slave model, assertions
  • Testbench integration
    • Testcase coding
    • Simulations and waveform analysis
  • Functional coverage analysis
  • Assertion coding and analysis

Enhance AXI3 VIP for AXI4 additional features

  • QoS signaling
  • Multiple region signaling
  • User-defined signaling
  • Low power interface

Introduction

  • About the protocol
  • AHB revisions
  • Operation

Signal Descriptions

  • Global signals
  • Master signals
  • Slave signals
  • Decoder signals
  • Multiplexor signals

Transfers

  • Basic transfers
  • Transfer types
  • Locked transfers
  • Transfer size
  • Burst operation
  • Waited transfers
  • Protection control
  • Memory types
  • Secure transfers

Bus Interconnection

  • Interconnect
    Address decoding
    Read data and response multiplexor

Slave Response Signaling

  • Slave transfer responses

Data Buses

  • Data buses
  • Endianness
  • Data bus width

Clock and Reset

  • Clock and reset requirements

Exclusive Transfers

  • Introduction
  • Exclusive Access Monitor
  • Exclusive access signaling
  • Exclusive Transfer restrictions

Atomicity

  • Single-copy atomicity size
  • Multi-copy atomicity

User Signaling

  • User signal description
  • User signal interconnect recommendations
  • UVC architecture
  • UVC components
  • UVC types
    • Master, Slave
    • Active, Passive
  • UVC test scenario listing down
  • UVC component coding
    • Driver, Sequencer, Monitor, Coverage, Environment
    • Interface, transaction, Slave model, assertions
  • Testbench integration
    • Testcase coding
    • Simulations and waveform analysis
  • Functional coverage analysis
  • Assertion coding and analysis
  • APB protocol introduction
  • Signal descriptions
  • Transfers
  • Operating states
  • Develop APB UVC for master and slave
  • APB master UVC validation using slave UVC
Course AMBA Protocol training, AXI VIP, AHB UVC and APB UVC Development
Duration 6 weeks
Course Start date 16/JANUARY
Schedule
Freshers Full week course
Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9AM to 1PM). Flexible lab sessions for US Students.
Weekdays sessions will be focused on course labs, interview preparation
Students also get support on complete project flow during weekdays as well.
Working professionals Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US)
8:30AM – 12:30PM (Theory session offered by trainer)
1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
Students will take the weekday tests and assignments from home.
New batch starts Every 16 Weeks
Fee INR 8500 + GST@18% (Classroom training)
Tool Questasim & VCS
Mode of training Classroom training at Institute(ORR, Banaswadi)
Online training using live training sessions
Tool Access Access to tool at institute for 12 months
Certificate Issued based on 50% assignment completion as criteria
Assignments 5
Trainer 14+ Years exp in RTL design & Functional verification
  • Exposure to any bus protocols like I2C, SPI, etc
  • Exposure to digital design concepts

Yes. Participant will gain exposure to following aspects

  • VIP development for AXI3 protocol
  • UVC development for AHB2 protocol
  • UVC development for APB protocol
  • Analysing AXI, AHB and APB timing diagrams in simulations
  • Functional coverage analysis
  • Assertion coding and debugging

Each session of course is recorded, missed session videos will be shared

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year
  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

Course Material Shared

  • AXI, AHB, APB protocol specifications
  • VIP/UVC code for AXI, AHB, & APB protocols
  • Short notes/checklist for each protocol
Experienced Trainer

Senior Teacher

4.9 Star Rating

5 Courses

Trainer Profile

  • Institute has multiple trainers handing front end domain courses. Average experience of trainers is 10+ years.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects

Target Audience:


  • Verification engineers with no prior exposure to any AMBA protocol.
  • Verification engineers looking for better career opportunities, and looking to improve their profiel
  • Engineering college faculty looking to enhance their VLSI skill set

₹9,000

₹10,000

20% off

10 hours to remaining this price

This course includes:
  • Full Lifetime Access

  • 30 Days Money Back Guarantee

  • Free Assignment

  • Free Presentation

  • Free Notes / Lab

  • Access on Mobile , Tablet and Laptop

  • Certificate of Completion

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

Course Registration