Systemverilog discussion forum


  • Please post queries from Systemverilog course; this will be a common platform for posting all SV queries.
  • Queries related to SV language constructs, VIP Development, TB Component coding.
  • Queries will be answered by both trainers and students.
  • Same page will be used for all the Systemverilog batches, so that queries from various batches are consolidated in single page.
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  1. Sreenivas Reply

    What is Singleton class?

    • vlsiguru Reply

      Type of class with is permitted to have only one object instance in whole TB environment. Ex: uvm_root is a singleton class since uvm_root top; is only instantiated once in TB

  2. viresh Reply

    Hi everyone,

    I could not attend the Mailbox class and now going through the code attached in labs. I have a doubt regarding mailboxes.
    In the LRM it is mentioned that a mailbox is created using method new(). In the code attached, the new() method is never called on mailboxes of producer and consumer. So how are they getting created?

    class consumer;
    eth_pkt pkt;
    mailbox#(eth_pkt) mbx;

    function new(mailbox#(eth_pkt) top_mbx);
    this.mbx = top_mbx;

    task run();
    for(int i=0;i<10;i++) begin
    $display("CONSUMER: getting transaction = %t",$time);

  3. admin Reply


    Mailbox is similar to FIFO in Verilog. Mailbox is created in Environment class, it is passed as a handle to both BFM & Generator. It will ensure that both point to same memory of mailbox.

    If we do new for each mailbox instance, we will be working with 3 different memories of mailboxes. It is similar to using 3 FIFO for connecting 2 components. Hence mailbox = new should not be done BFM & Generator, it is only done in Env class, handle is passed to both BFM & Generator.

    Hope it answers your query.

    • Viresh Reply

      Got it.

  4. admin Reply

    Queries from a student(SV_JULY2017 Batch):?

    1. Difference between BFM and Driver?
    [ANSWER] Both are same, just that BFM is used in SV based testbenches, Driver used in UVM based testbenches.
    BFM : Bus Functional Model(it models a bus functionality)
    Driver: Drives the transactions or packets on to DUT.
    At the end, both achieve same functionality.

    2. In the Ethernet packet data example the length is defined 2 octets (16 bits) and the payload if from (45: 1500 octets). So when we declare the length we declare it with logic data type of 16 bits means it can take any 4 logic values and we define payload as queue because we do not know its size and we make it as a 8 bit. Suppose if we have 10 octets means that there are 80 bits in the payload and as per you the no of octets in payload is the length and in the constraint also we call like
    Constraint payload_c {
    What confusing me is that logic[15:0]len it means that there are 16 bits in the length variable .

    [ANSWER]: Packet is framed in terms of bytes, all the fields in Ethernet frame are multiples of Octet in their sizes. Ideally speaking, it is possible to have 12 bit lenght variable to accommodate all sizes of packet(40 to 2047 including jumbo packets). However 12 bits will be equal to 1.5 octet. We do not want to view packet like 1.5 octet. Hence length is stored using 2 octets.

    3. Function void post_randomize();
    function bit[31:0]calc_crc();
    return 32’h123456789;
    the use of post randomize and explain the above code that how it works

    [ANSWER] : Post_randomize is used to do the calculation post randomization completion. That is calculation of variables which are not random, but are dependent on random values generated during randomize. In our example, that happens to be CRC, we are using post_randomize to calculate CRC. We did not have time to implement CRC calculation logic in class, hence we assigned a fixed value to CRC(in calc_crc method). Ideally it should have been completed implemented to get real CRC value.

    4. In the top module we write $value$pulsargs(“testname=%s”,eth_pkt::testname);
    Explain this statement and its reference with the code

    [ANSWER] : Above System function is used to get the inputs from elaboration command. When use calls above method, tool looks for command line options of vsim command.

    If we use vsim as below:
    vsim work.top +testname=xyz_test

    $value$plusargs will read above argument into “eth_pkt::testname”. This variable is used in post_randomize to decide how randomization should be done.

    5. CRC 3800839290 if we divide it with 457 then we get remainder from 0 to 456 then the number become 380039290xxx explain it ?

    [ANSWER] : if we divide a number with 457, remainder is from 0 to 456, same is just used as XXX in above example. XXX can be anything from 0 to 456. XXX means that remainder can be up to 3 digits.

  5. Viresh Reply

    Is there a way to iterate over a mailbox without removing the elements from it? I am trying to print the elements present in the mailbox.
    The get() method removes the elements, whereas the peek() methods always points to the same element.

    • admin Reply

      There is no way to get all elements from mailbox without removing elements.

  6. Anshu Reply

    I would like to know the submission date for Assignment 1 for SV and Verilog?

    • admin Reply

      T : Systemverilog Batch Start Date
      T+2 week : 1st Assignment submission
      T+3 week : 2nd & 3rd assignment submission
      T+4 week : 4,5, and 6th assignment
      T+5 week : 7 to 10th assignment
      T+6 week : 11 to 14th assignment
      T+7 week : 15 to 17th assignment
      T+8 week : 18 to 19 th assignment
      T+9 week : 20th assignment
      T+11 week : 21 to 23rd assignment

      3 assignments every week.

  7. nikitaaggarwal2794@gmail.com Nikita Reply

    Hello Sir,

    I had a few doubts from last week’s lecture of SV.
    1.) When I extend base class to make derived class for eg: there is static variable count. I make one instance of base and one instance of derived class so my count output from simulation is 2. So my question is do static variables also get extended to derived classes ?

    2.) What exactly do we mean by dynamic polymorphism.

    3.) What are differences between copy by handle,shallow copy and deep copy as in advantages and disadvantages ?

    4.) Where is pack and unpack used in real life example ?

    Thank you

    • admin Reply

      Q1: Yes. Static variables are also part of derived class.
      Q2: Dynamic polymorphism is not supported in SV. It is a concept where methods are defined with different argument list in different derived classes. Which object’s method definition to use is decided based on the calling method arguments.
      Q3: We have discussed this in detail in class. Please refer to class notes.
      Q4: Pack & unpack are used while working with every peripheral communication protocol like Ethernet, USB, PCIe. Pack is used to pack the packet fields in to Queue of bytes, these bytes are driven one by one to design. Unpack does the reverse, it is used to collect the bytes into byteQ. The byteQ is unpacked in to packet object.

  8. nikitaaggarwal2794@gmail.com Nikita Reply

    What is the difference between output argument, input argument and return data of a function?

    • admin Reply

      function bit calc_sum(input int a, input byte b, output byte c);

      bit : return data of function
      a, b : input arguments
      c : output argument

  9. Nikita Aggarwal Reply

    In the eth_pkt example of last session, I have doubts in the eth_bfm code and eth_env code. In eth_bfm,only 10 transactions are there, then why use forever begin ?
    In eth_env, Why using fork-join ? Why have processes in parallel? Why not have in sequential manner ?

    Thank you Sir.

    • admin Reply

      1. why forever used in BFM?
      – the test ran is generating 10 pkts, another test we run may generate different number of pkts. To take care of this use forever loop in bfm. mbox.get is blocking method. Hence BFM will stop. When user calls $finish simultion will anyway finish.

      2. fork..join
      – all the components in TB should run concurrently.
      – TB can’t work like one components starts, then stop, then another components starts, etc. All have to run in parallel.

  10. Nikita Aggarwal Reply

    This is a Verilog doubt. I did not understand handshaking and why are we using it in memory code? After ready_o is asserted then immediately valid_i is made 0 then there will be no valid read/write Tx so I did not understand this particular flow of code in testcase back door write front door read.

    Another doubt in verilog is related to D flip flop behavioral code without reset signal. I did not understand why output is changing at negative edge of clock inspite of specifying the sensitivity list with posedge.

    module dff(q,clk,d);
    input clk,d;
    output reg q;
    always @(posedge clk) begin
    q <= d;

    `timescale 1ns/1ns
    `include "dff.v"
    module tb();
    reg clk,d;
    wire q;
    reg [15:0] sequence;
    integer i;
    dff dut(q,clk,d);
    initial begin
    forever #1 clk= ~clk;
    initial begin
    for(i=0;i<16;i=i+1) begin
    $display("time=%t clk=%b d=%b q=%b",$time,clk,d,q);

    Time=0 clk=1 d=1 q=x
    Time=1 clk=0 d=1 q=1
    Time=2 clk=1 d=1 q=1
    Time=3 clk=0 d=1 q=1
    Time=4 clk=1 d=0 q=1
    Time=5 clk=0 d=0 q=0
    Time=6 clk=1 d=0 q=0
    Time=7 clk=0 d=0 q=0
    Time=8 clk=1 d=0 q=0
    Time=9 clk=0 d=1 q=0
    Time=10 clk=1 d=0 q=0
    Time=11 clk=0 d=1 q=0
    Time=12 clk=1 d=0 q=0
    Time=13 clk=0 d=0 q=0
    Time=14 clk=1 d=1 q=0
    Time=15 clk=0 d=1 q=1

  11. Niranjani S Reply

    Hello sir,
    we use streaming operator to pack stream of bytes. can the same operator be
    used to unpack also ?

    • admin Reply

      No. It has to be done manually, there is no operator.

  12. chaithanyakatha@gmail.com Chaithanya Reply

    static cast is not working,can anybody explain with syntax?

    • admin Reply

      int a;
      byte b;
      a = 10;
      b = byte'(a); //syntax

  13. nikitaaggarwal2794@gmail.com Nikita Reply

    Hello Sir,

    I had a doubt in unions.Could you please tell me how to form a union and initialize its elements.

    Thank you

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  15. aravind767@gmail.com aravind Reply

    Can anyone explain the use of “srandom”?

  16. aravind767@gmail.com aravind Reply

    The randomization construct $urandom has an optional seed argument.

    The seed can also be specified in the vsim command using vsim -sv_seed 573497.

    What is the difference in the above two ways?

  17. shilpa.medipalli@gmail.com shilpa Reply

    static casting is not working with arrays

    • Niranjani S Reply

      Hi , static casting works with arrays. Try it with loop condition.

  18. ganeshrahate900@gmail.com Ganesh Reply

    Hi ,
    as we know constraint are not procedural and they do not allow for loop
    but they allow foreach so how foreach is executed by the system verilog solver does ,
    does it first randomize complete array and then apply the constrains and change the values because in that way it will follow the non procedural aspect
    but if goes on from first element to second then it will be procedural thing

    thank you

  19. bnaparna7@gmail.com aparna Reply

    when i tried to add signals to log i am getting an error which says:
    (vish-4014) No objects found matching ‘/top/*’.
    Can anyone help me to fix this.?
    Thank you.

  20. vasumurthy.p22@gmail.com vasu Reply

    Hello Sir,
    Im working on “verification of Memory controller”, im having confusing in using signals of memory interface(signals are defined in mem_intf.sv file)(mc_ack_i;
    I’m not finding CLEAR explanation about these signals in the “mc_doc” file also.I want to know exact operation of each signal wrt time. Where do i find complete description & timing diagram of all these signals??

    Thank You

  21. astakar.lokesh@gmail.com Reply

    Hi I am trying to access the enum variable in my top module which is defined in nested class, but Questasim is throwing an error if I access as shown below:

    class eth_pkt;

    class my_pkt;

    class my_sample;

    typedef enum {RED,BLUE,GREEN} color_t;

    static color_t colour=GREEN;


    my_sample sam;

    function new();


    my_pkt m_pkt;

    function new();
    m_pkt = new;



    module color_top;


    $display(“Colour= %s”,colorr.name);


    Is this a wrong way of accessing or assigning variables? Please let me know?

  22. astakar.lokesh@gmail.com Reply

    Hi Sir,

    As part of the assignment, I was trying assign a enum variable in top level module as shown below, but throws an error saying that Illegal assignment? wanted to know if this is the right way to access and assign the variables

    class eth_pkt;

    class my_pkt;

    class my_sample;

    typedef enum {RED,BLUE,GREEN} color_t;

    static color_t colour=GREEN;


    my_sample sam;

    function new();


    my_pkt m_pkt;

    function new();
    m_pkt = new;



    `include “eth_pkt.sv”
    module color_top;

    color_t colorr;

    $display(“Colour= %s”,colorr.name);


  23. astakar.lokesh@gmail.com Reply

    Hi Sir,

    with respect to an Assignment 8(Datatypes) , when I try to assign and access the enum type variable outside the nested class in top level module, simulator throws an error saying it cannot assign value to enum variable? Any suggestion how to go about this?

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