– theory and lab sessions


  1. function: sum
    inputs: a , b (integer)
    output is return of the function
    Please implement this function in Verilog. function integer sum(input integer a, input integer b);
    sum = a + b;
  2. two integer arrays
    integer intA1[5:0];
    integer intA2[5:0];
    integer intA3[5:0];
    write a for loop to call above ‘sum’ function, to add elements of intA1 and intA2
    o put the output to intA3
    • how to use a function
    integer i;
    for (i = 0; i < 5; i=i+1) begin
    intA3[i] = sum(intA1[i], intA2[i]);
  3. what is the intention of TB development?
    o to check the design behavior matching as per the speficiation
    o what do we do in TB?
    o generate the stimulus(scenario or inputs) and drive those inputs to the design
    o collect the outputs and compare them against expected output values.
    o ex:
    2×1 Mux
    o TB using Verilog
  4. what is the intention of TB development?
    o this intention of TB development is same in every language
    o Verilog or SV or UVM
    o SV provides more constructs
  5. difference between == and === operator?
    o == : logical equality operator
    o === : case equality operator reg [3:0] a, b;
    reg c;
    a = 4’b10zx,
    b = 4’b10zx,
    c = a == b; => c = 1’bx; (unknown)
    c = a === b; => c = 1;
    – a case equality with b
  6. GVIM
    function recording
  7. Simulator
    o compilation?
    o elaboration?
    o adding signals to the wave?
    o simulation? o options at different stages
    o defining a macro? compilation
    vlog +define+WIDTH=10 +define+DEPTH=20
    o arguments to be read using $value$plusargs => elaboration
    vsim +count=20 +seed=138933
    //+ arguemtns: user has to manually use $value$plusargs
    vsim +count=20 -sv_seed 138933
    o what is meant by +argument and -argument?
    +argument: must be read using $value$plusargs
    -argument: tool automatically reads those arguments
    vsim -novopt -sv_seed 484389
    o tool automatically read -novopt, -sv_seed
    -novopt: run elaboration without optimization
    -sv_seed: user is providing me a seed to use for randomization purpose
    o pass a seed value? elaboration time
  8. 7 weeks
    o 15 assigments
    o 2 assigments per week
    [email protected]
  9. Functional verification overview
    o why we are learning SV?
    o why SV is easier compared to Verilog?
  10. what is the primary objective of functional verification engineer?
    o check the design functionality against the design speficiation
    o “catching as many design bugs as possible”
  11. VLSI design flow : 12 steps
    o product requirements o RTL design
    o RTL integration
    o Functional verification

    o DFT
    o Synthesis
    o physical design
    o STA
    o Layout o fabrication
    o post silicon validation
  12. driving factors of functional verification
    o less time in setting up TB
    o more time in developing testcases and debugging failing testcases
  13. USB controller verification
    Verilog: 6 months
    SV : 4.5 months
    o SV provides more language constructs, which makes all the aspects TB development easier
    UVM : 3.5 months
    o UVM provides pre-implemented classes, which user can use to develop TB components
    o summary: user don’t need to develop components from scratch.
  14. summary
    o functional verification: TB development is not the primary goal
    o main objective: catch as many bugs as possible
    o spend a lot of time on testcase development
    o spend minimal time on testbench development
    o SV and UVM are making it happen
  15. Verilog
    o most of the TB goes in to single module
    o task and function based code.
    o Memory testbench in Verilog
    o task, function were used to make code resuable
    o Verilog testbench
    o do everything in same module, but do them as separate task and functions.
    o task, functions is the only and only the best thing we can do in Verilog. SV:
    o do everything in different components(not in same module)
    o what is that everything refers to?
    o generation of scenario ===> scenario generator
    o driving scenario to the design ===> driver (BFM)
    o monitoring design inputs and outputs ===> monitor
    o doing various types of coverages(functional coverage) on the design inputs ==> coverage
    o predict the design output ===> reference model(generates the reference output)
    o compare this output with actual design output ===> checker
    o keep track of how many matches and mismatches, based on that report the test status ===> scoreboard
  16. SOmeone gives me above TB architecture diagram, ask me to develop in Verilog
    o It is very difficult to do.
    o Verilog doesn’t recommend(support) a TB architecture with a lot of TB components
    o major reason: connecting those components is at port level, it is difficult to do.
    o SV is good at developing these kind of TB
    o modular TB architecture
    o kind of TB developing style where whole functionality is divided in to multiple components.
  17. By product of modularity is reusability.
  18. what is the beneftis of modular testbench components?
    o project management becomes easier
    o since work can be easily distributed
    o one component implementation issues doesn’t implement other components
    o helps with code reuse
    o developing new TBs using existing TBs becomes easier

Simple design:
o 2×1 mux => Verilog Tb is lot easier compared SV TB
o If we take a complex design (USB controller) => Verilog Tb is very difficult to do, SV TB is relatively eaiser.

  1. DIfference between SV & UVM
    o pizza making
    o pizza base bread (make it, buy it)
    o make the pizza
    o UVM will tell in what propotion to add, when to add.
  2. functional ‘verification’
    o Backend engineer: verification => physical verification
  3. various components of the TB
    2 categories
    components used for ‘scenarion generation and driving to the Design:’
    o generator
    o BFM(driver)
    o coverage

components used for ‘checking the design behavior:’
o monitor
o reference model
o checker
o scoreboard
o assertions
o slave model

next 3 months of training is focused on how to develop above 9 compoents efficiently.
  1. when to close FV?
    o 100% testcases passing
    o 100% functional coverage
    o 100% code and assertion coverage
  2. developing modular testbenches
    • verilog, VHDL, SV, UVM
      • Verilog and VHDL are not good for modular testbenches.
      • SV & UVM are right choice for modular testbenches.
  3. what is that makes them right for modular testbenches?
    o ‘Object oriented programming’ : classes
    o for any engineer who does programming, OOP always takes your programming to a next level.
    o Python, PERL, C++, SV anything => Why people use OOP => ‘modular’ style
    o when you are learning OOP in SV => Give your best possible effort
  4. Things will move quickly => spend enough time to keep up with the training pace
  5. SV language basic concepts
    o how it differs from Verilog?
    o data types
    o two types
    – static data types
    o verilog only supports static data types
    – dynamic data types
    o system verilog supports both static and dynamic data types
  6. ethernet protocol
    ethernet frame: haivng length of 42 to 1500 octets Verilog:
    reg [7:0] payload[1499:0]; //we need to take in to consideration the biggest possible size SV:
    reg [7:0] payload[$]; //Queue
    reg [7:0] payload[]; //Dynamic array
    o if we want to create frame of 100 octet payload size
    payload = new[100]; //only 100 element space will be used
    payload = new[200]; //only 200 element space will be used
    payload = new[10]; //only 10 element space will be used, 190 element space gets freed up
    payload.delete(); //whole space gets freed up
    • which one is efficient in memory utilization?
      o SV
  7. payload = new[100]; //allocate enough memory to store 100 elements
    • memory allocation
    • whenever we work wtih dynamic data type
      o we need to explicitly tell how much memory to allocate.

29Q. thats is this similar to override concept?

  1. Verilog has only static data types
    o not efficient for memory utilizaiton SV: mix of both data types
    o it is very efficient for memory utilizaiton
  2. how do we know which constracts are static and which are dynamic?
    integer => static
    o memory gets allocated at compile time
    o integer based variables require 32 bit of space
    byte b; => static => 8 bit space integer intA[]; //dynamic array

32Q. new [100] –> new [200] means memory will incresed or it will be delete previous 100 loactions ?
intA = new200; //it will retain exisitng 100 location values of intA
intA = new[200]; //it will create all 200 elements with default values(doesn’t retain existing values)

  1. different phases of data type usage
    • definition
      o language provided
      o user defined
    • instantiation
    • creation
    • randomization
  2. integer a; typedef reg [3:0] nibble_t; //4 bit vector => nibble_t is an example of user defined data type
    nibble_t b; //b is 4 bit vector
  3. integer a;
    a = new(); //not required, because 32 bit memory is already allocated to ‘a’
    o for all static data type, we don’t need to use new byte b;
    b = new(); //not required integer intA[];
    intA = new[5]; //dynamic => hence we are using new to allocate memory
  4. new gets used in different styles of for different dynamic constructs
    eth_pkt pkt = new();
    int intDA = new[200];
    – without doing new, we can’t use intDA
  5. randomization
    o for a verification engineer, why randomization is important?
    o same electronic device => gets used differently by different people
    o kind of inputs we apply to the devices are random in nature.
    o how to get similar behavior during the verififcaiton? randomization o Verilog
    $random, $urandom_range(100, 200) o SV
    $random, $urandom_range
  6. Verilog
    o no pre-impelmented methods in Verilog SV:
    o every construct has a lot of pre-impelmented methods
    o construct: mailbox (~similar to FIFO)
    o FIFO in verilog
    module FIFO(ports); //we need to do from scratch
    parameter DEPTH=16;
    //funcitonality => 100 lines of code
    endmodule FIFO #(.DEPTH(100)) u1(port connection); @(posedge clk); wdata=$random; wr_en = 1; so on o SV mailbox mbox = new(100); //mbox with size 100 gets allocated(created) mbox.put(15); mbox.put(37);

39Q. This mailbox can we use in design also?
o no
o mailbox is non-synthesizable
o it is only TB development purpose

40Q. SV can be used for design?
– yes
– SV has constructs which are for design purpose
o always(verilog) => always_comb, always_ff, always_latch(SV)
– SV has otehr constructs which are for testbench development purpose only
o OOP, dynamic array, associative array, queue => TB development

41Q. Is mailbox just like queue?
o mailbox is simular to FIFO
o queue : many things are possible
o push front, push back
o pop front, pop back
o insert
o shuffling
o reverse

o mailbox behvior is subset of queue behavior
  1. int intQ[$];
    intQ.pop_front(a); //wrong usage
    a = intQ.pop_front(); //correct usage intQ.insert(10); //wrong usage
    //we should be giving two arguments
    intQ.insert(3, 10); //correct usage
    at 3 index, insert 10
  2. if method is a function, then it will return of funciton
  3. if method is a task, then it will return of task output argument



  1. Introduction to SV
    o how SV differs from Verilog
  2. SV advantage comes majorly due to lot of added constructs
    o Object oriented programming
    o data types
    o operators
    o procedural statements
    o inter process synchronization constructs
    o functional coverage constructs
    o assertions
    o DPI
    o interface, modport, clocking block
  3. SV language basic concepts
    • data types
      o static data type
      o dynamic data type
    • different stages in which data types are used
      o definition
      o instantiation
      o creation
      o randomization
    • SV implements all the constructs, also provides methods(task and functions) to use these constructs.
      queue: push_back, push_front, pop_back, pop_front


  1. Memory Allocation and De-allocation
  1. Who allocates the memory?
    o memory is allocated by the simulator
    o starting location of the memory allocated, is called as ‘handle’
  2. mailbox mbox = new(); //allocating memory to the mbox
  3. C programming
    int a;
    *a => pointer to the memory allocated ‘a’

There is no *a concept
a will refer to both value and pointer(handle) based on the context, how it is getting used.

  1. string a; //a is not a SV keyword
    string cover, class; //cover and class are SV keywords
  2. dot convention in Verilog
    o XMR : Cross module reference
    o Verilog only supports
    module name, task, function, process name(label) module top; initial begin : P1 begin: P2 integer count; end endtask endmodule top.P1.P2.count o SV: XMR can be for any type of variables
    o Backdoor access when we use it on RTL code.
  3. `include “fa.v”
    o fa.v code gets included in to current file /*
    start of comment
    nexxt comment
    last comment
  4. prototype
    o model of actual device function integer sum(input integer a, input integer b); ==> called as function prototype
    o prototype tells us, how to use the function. p,q => r
    r = sum(p, q);
  1. arrays
    o static
    int intA[5:0]; //6 is the size
    int intA[-3:-7]; //possible
    o dynamic

10Q. is that logic works if two array sizes are different??
assert (wordarr1 == wordarr2) $display(“matched”);
o both arrays should be of same size
o all the elements should match

  1. $display(“wordarr1=%p”,wordarr1);
    packed printing
    printing everythin in one place(line)

assert => it tells us which line and file name from which error is getting reported.
o we can clasify the severity

assert(expression) $display(P1);
else $display(P2);

12Q. warining can’t be used outside asserts blocks ?
o $warning can be used outside of assert

13Q. practical applications for array (dynamic/associative/queue) ? mean good way of using depeding on situaion?
o given a speicif cTB compoent or requirement, which type of array will be suitable.

  1. Verilog drawbacks
  1. DMA controller functional verification
    6 months project
    end of 2 months: what is the progress with project?
    o Functonal coverage: 72%
    o Code coverage number: 65%
    – we are 70% of the project completion
    o assertion coverage
  2. Verilog, every thing in static data type
    reg [7:0] payload[1499:0]; //we always declare of 1500 size only
    reg [7:0] payload[];
    payload = new[100];

function integer sum(module sample1, module sample2); //not possible
//task and function arguemtns can only be eitehr integers and vectors

function integer sum(eth_pkt pkt1, eth_pkt pkt2); //possible
o objects can be passed as arguemtns of task and functions => provides lot of flexiblity

  1. SV has concept OOP, which makes code reuse possible
  2. agenda



  1. How we can pass dynamic array to a function or task?
  2. please don’t initialize values and run ?


  1. Verilog is called as HDL
    o primarily Verilog was developed for describing the design behavior
    o since design were simple, testbench was also developed using Verilog
  2. Complexity of design
    o number of blocks going in to the design
    o complexity of blocks
    o protocols involved
  3. Verilog langauge is a subset of SV
    o I am doing some design development using Verilog
    o I am doing some design development using SV => same as above line
  4. SV design constructs = Verilog + some additional design constructs
  5. OOP
    Verilog: module and task based langauge
    o everything in Verilog is viewed in terms of module, task and functions.
    SV :
    o whole environemtn is viewed as set of components, each of which can represented as an object
  6. Vera
    2000-2002 : Vera was developed
    Vera is the first OOP functional verification language
    VCS simulator supports Vera compilation and simulation

specman e => Cadence aquired

IEEE 1800 standard => C, C++, Vera, Verilog => SV

always @() begin //intention is combinational logic => it ends up infering latch behavior

always_comb @() begin //surely infers combinational logic => Lint checks will catch that incase any coding mistakes

always_latch @() begin //surely infers latch logic =>

8Q. what is Lint check?

module top;
if (a == 10) begin
//Lint checks will tell me that, we have missed else condition above code.

  1. Literals
    o guidelines that needs to be followed while assining the values string name;
    name = vlsi; //wrong, we din’t use “”
    name = “vlsi”; //correct o int intA[3:0];
    intA = 1,2,3,4; //wrong
    intA = {1,2,3,4}; //correct
    o above rule will be called as ‘array literal’ o int intA[2:0][1:0]; //multi dimensional array
    intA = {{1,2}, {3,4}, {5,6}}; o integer a;
    a = u; //wrong
    a = 10’h10zx; //correct o real r;
    r = 2.3;
  2. logic is new data type in SV
    o similar to reg

11Q. Packed Printing is valid for unpacked array also?
unpacked array: array in Verilog

12Q. what is the difference ‘{ and {

int intA[4:0][2:0];
intA = ‘{5{‘{1,2,3}}};

14Q. Can we change the indexing starts?

  1. byte b;
    b = 10; //we will call byte as an integer based data type bit [3:0] a;
    a = 15; //bit also as a integer based data type
  2. if we do %0h that 000 will not come.. i think
  3. b=0xx1001zzzz
    by keeping MSB print as 0 => indicating that all upper most bits [31:11] positions will be 0’s
  4. signed means only positive numbers?
    • and – also

19Q. how can we represent 11100010 as -30
30 : 16+8+4+2
2’s complement: 1’s complement + 1
8’b1110_0001 + 1 = 8’b1110_0010

2’s complement representaiton:

, but you said for signed numbes, msb represents signed bit?

  1. verilog
    reg, wire
    reg: represent discretely driven element
    wire: represent continously driven element
    = reg and wire are design specific concepts class tx;
    reg a; //
    //2 new data types are introduced : bit, logic
    bit: 2 state variable
    logic: 4 state variable
  2. logic is synthesizable
  3. difference between reg and logic
    o multiple drivers =>
  4. reg should be used in prcedural block but logic is flexible?

24Q. Why the size of integer is mentioned as >= 32? Can you mention one example where it is greater than 32?

  1. time
    stores value in integer format realtime
    stores value in real format



  1. Literals
  2. Integer based data types
    o 2 state or 4 state
    o size
    o signed or unsigned
    o Verilog or SV
  3. int a;
    $display(“a”); //0
    integer a;
    $display(“a”); //x anytime we declare an int variable, we don’t worry about initialization
  4. bit b; //0
    logic b; //x
  5. time and realtime


  1. void
    o function return_data_type function_name(arguments);
    endfunction o function void function_name(arguments);
  2. assert(anything);
    if anything(any expression) evaluates to ‘1’ => assert prints success message
    if anything(any expression) evaluates to ‘0’ => assert prints failure message void'(pkt.randomize());
    converting 1/0 to void format => ignore the output.
  3. string is an exception, where we don’t need to use ‘new’ constructor to allocate memroy
    string name;
    //name = new(); //
    name = “verilog”; //it automatically allocates 7 char spaces for name(7*8 = 56 bits)
    name = “system verilog”; //it automatically resizes to 14 char spaces for name.
  4. len : returns number of chars in string
    putc: put char in to the string at a speciifc location
    getc: get a char from string at a speciifc location
    toupper: convert all chars to upper case
    tolower: convert all chars to lower case
    compare: compare 2 strings
    icompare: compare 2 strings with case insensitive
    substr: returns a sub string form string
    atoreal: ASCI to real conversion
    itoa: integer to ASCI conversion

5Q. is there any method to get array length or size?
Dynamic array: len
Queue: size

6Q. putc is replacing the character. Do we have any method to insert character?
– ex: to insert space at 6th index

  1. concept of special chars
    new line: \n
    tab space: \t
    to print \ itself: \
    to print / : \/
    to print ” : \”
    to print % : %%
  2. compare
  3. TB with variable number of sub_env’s, each sub_env should have unique name.
    sub_env_0 : “sub_env0”
    sub_env_1 : “sub_env1” 10 sub_env: sub_env0 to sub_env9
    50 sub_env: sub_env0 to sub_env49
  4. string
    • insert, delete (not provided by SV language)
    • reverse

11Q. Inplace of C we can take any other byte name also right ?

  1. Arrays
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