SES#1

course overview:

  1. SV training
    3 aspects
    o SV language training
    o 7-8 weeks => expert with SV language
    o strong foundation with SV language constructs
    o AXI protocol and VIP development
    o 2-3 weeks
    o give exposure to coding and TB component development
    o Industry standard project
    o 5 weeks
    o give exposure to entire verification flow.
    o overall duration: 14 to 16 weeks
  2. Most of requirements
    Ver+SV+UVM
  3. schedule is similar to the one we had for Verilog

Notes:

  1. why we need SV?
    o Verilog has few constructs(ex: for, always, etc), SV has lot of constructs
    o lot of constructs => more options in developing TB components => Hence SV makes TB development easier
  2. WHy we are moving SV?
  3. how to run with Questasim
    vlog top.sv
    vsim
    add wave *
    run -all
  4. SV language concepts
    o
  5. SV language basic constructs
  6. static and dynamic data types
    any memory allocation that happens at compile time(vlog top.sv) itself, it is called as ‘static’
    any memory allocation that happens at run time(run -all), it is called as ‘dynamic’
  7. Anytime we work with dyanmic data types, always use ‘new’ to create the memory
  8. SV = static data types + dynamic data types
    Verilog = static data types (no dynamic)
  9. Different phases of data type usage
    Definition:
    • Language provided
    • User defined data types
      Instantiation
      Creation //for static datatype, Creation is not required(new)
      Process of allocating memory to the data variable
      ex: pkt=new();
      Randomization
  10. integer a; //static or dynamic?
  11. Constructs and Pre-implemented methods
    FIFO in Verilog
    user defined module?
    did we get FIFO defintiion from Verilog alngauge?
    everything in Verilog is User defined.
  12. in SV, language itself implements lot of things for us.
    FIFO(Verilog) => mailbox(SV)
    what operations we can do with FIFO?
    – read
    – write
    – reset
    – get the size of FIFO
    SV impelemtns above functions by default, user don’t need to implement these methods.
    – user just needs to understand, how to use these methods.
  13. Verilog, how much time taken to develop to FIFO?
    o 2-3 hours
    o in SV, we don’t need 2-3 hourse, since language itself provided the mailbox(~FIFO)
    – 2 minutes to acehive same

14
mbox = new(20); we can put maximum of 20 elements in to the mailbox
mbox = new(); we can put any number of elements in to the mailbox

  1. SV : common shared memory concept
  2. How Task, functions make Verilog code resuable and readable?
    o Mmeory TB => write_mem, read_mem
    o Same concept applies in SV also.
    o as much as possible, use task and functions while developing the code.
  3. mailbox
    new, put, get, try_put, try_get, peek, num
  4. Queue
    push_back, push_front, pop_back, pop_front, shuffle, insert, reverse, size
    • we don’t need to learn, how to implement above methods.
    • we only need to know, how to use these methods
  5. write a function, two input integer arguments(a,b), add numbers(a, b), return as function return value
    name of function : sum

function integer add(input integer a, input integer b);
add = a + b; //Verilog
return a + b; //SV
endfuction

integer p, q, r;
use above function to add p, q and assign to r
r = add(p, q);

20.
function void add(input integer a, input integer b, outout integer c);
c = a + b; //SV
endfuction

integer p, q, r;
use above function to add p, q and assign to r
add(p,q,r);

  1. homework
    Assignment:
    Declare an array of word(reg [15:0]) data type, array size of 10. Fill it with random number between 20 to 30
    Declare another array of word data type, array size of 10. Fill it with random number between 20 to 30
    Write a logic to Compare elements of both the arrays.
    Assignment:
    Declare an array of string data type, array size of 10. Assign elements with names from str1 to str10
    Declare another array of string data type, array size of 10. Assign elements with names from str1 to str10
    Write a logic to Compare elements of both arrays.

Dynamic Arrays
Size is allocated at the run time. Size can be changed during the run time.
Declaration
integer intDA[ ]; //Dynamic array
integer intAA[*]; //Associative array
integer intAA[string]; //Associative array
integer intQ[$]; //Queue
Assignment:
Declare a dynamic array of word data type, allocate size of 10. Fill it with random number between 20 to 30
Declare a fixed size array of word data type, array size of 10. Fill it with random number between 20 to 30
Write a logic to compare elements of both arrays.

SES#2

1.
module sample1;
module sample2;
function sum(sample1 s1, sample2 s2); //Not possible
endfunction

class sample1;
class sample2;
function sum(sample1 s1, sample2 s2); //possible: objects/class can be task/function argeumtns
endfunction

2.
SV : Hardware Description & Verification Language (HDVL)
o can be used for verification purpose also
Verilog: HDL

  1. Vera is HVL developed by Synopsys.
    o 2000 – 2005 time frame
    o Companies prefer using Vera(OOP language), compared to Verilog for TB development
    o when they use Vera, they have to use VCS tool(only that tool support)
  2. homework
    • example to show difference between bit and logic
  3. range of int
    int a;
    int is 32 bit signed variable.
    -231 to 231-1

n bit signed variable: -2n-1 to (2n-1) – 1

shortint: 16 bit
– decimal format : -32768 to 32767

function void print(); //this function does not return any value. Use void
$display(“a=10”);
//not retutrning anything
endfunction

  1. string str;
    str = “verilog”; //7 bytes
    str = “system verilog”; //14 bytes
    str = “”; //0 bytes
  2. String comparison
    comp_f = 0 => compare has matched
  3. how to reverse a string. => homework
    for, putc => Hint

SES#3

  1. string data type
    o sting methods
  2. string reversal

Notes:

  1. Operators
    • Verilog operators
    • SV added operators
  2. streaming Operators
    o ethernet frame : preamble(56), SOF(8), DA(48), SA(48), LEN(16), PAYLOAD(46-1500 bytes), CRC(32)
    o data transfer between laptops will happen through Ethernet frames. 1st clock cycle
    preamble[55:48] data will go
    2nd clock cycle
    preamble[47:40] data will go
    3rd clock cycle
    preamble[39:32] data will go
    so on sof will be sent
    DA will be sent
    so on
  3. convert ethernet frame fields in to Queue of bytes.
    o take one byte from queue every clock cycle and drive it to the interface.
    o when we drive all the bytes, whole packet would be transmitted. byte byteQ[$];
    byteQ.push_back(preamble[55:48]);
    byteQ.push_back(preamble[47:40]);
    byteQ.push_back(preamble[39:32]);
    so on
    • issue: this will become very long.
      streaming operators:
      byteQ = {<>byte{preamble, sof, da, sa, len, payload, crc}};
      back of QUeue? crc[7:0]
      front of QUeue? preamble[55:48]
      analogy:
      o cricket match streaming

nibble:
byte byteQ[$];
byteQ.push_back(preamble[55:52]);
byteQ.push_back(preamble[51:48]);
byteQ.push_back(preamble[47:44]);
so on

  1. multiply with 16
    what shift and how many? LS, 4
  2. multiply with 128
    what shift and how many? LS, 7
  3. divide with 64
    what shift and how many? RS, 6
  4. multiply with 65 (64 + 1)
    a << 6 a << 0 sum of above 2
  5. multiply a with 37 (convert 37 to addition 2** numebr)
    a << 5 (32)
    a << 2 (4)
    a << 0 (1)
    —–
    add 37

9.
i++ => post inrmente operator

10.

SES#4

  1. Book shelf
    12 books
    14 pages
    10 lines
    9 Englishwords
  2. totally how many words in book shelf = 121410*9
  3. if we give unique address to each book, how to declare the book shelf

word [13:0][9:0][8:0] book_shelf [11:0]; //if we give unique address to each book

  1. if we give unique address to each page, how to declare the book shelf
    o how many addresses are required in total = 12*14
    word [9:0][8:0] book_shelf [11:0][13:0]; //if we give unique address to each page
  2. if we give unique address to each word, how to declare the book shelf
    o how many addresses are required in total = 121410*9
    word book_shelf [11:0][13:0][9:0][8:0] ; //if we give unique address to each word
  3. if we give one address to whole book shelf, how to declare the book shelf
    o how many addresses are required in total = 1
    word [11:0][13:0][9:0][8:0] book_shelf;
  4. I want to refer to 7th book, 8th page, 6th line
    book_shelf[7][8][6]
    how many words does it represent? 9 words
  5. I want to refer to 5th book, 4th page, 9th line, 7th word
    book_shelf[5][4][9][7] => how many words? 1 word
  6. book_shelf[5] => how many words? 14109

multi_arr='{‘{‘{10, 9, 8, 7}, ‘{9, 8, 7, 6}, ‘{8, 7, 6, 5}}, ‘{‘{9, 8, 7, 6}, ‘{8, 7, 6, 5}, ‘{7, 6, 5, 4}}, ‘{‘{8, 7, 6, 5}, ‘{7, 6, 5, 4}, ‘{6, 5, 4, 3}}, ‘{‘{7, 6, 5, 4}, ‘{6, 5, 4, 3}, ‘{5, 4, 3, 2}}, ‘{‘{6, 5, 4, 3}, ‘{5, 4, 3, 2}, ‘{4, 3, 2, 1}}, ‘{‘{5, 4, 3, 2}, ‘{4, 3, 2, 1}, ‘{3, 2, 1, 0}}}

multi_arr[4][2][1]? 7
multi_arr[0][1][3]? 4
multi_arr[0][0][0]? 0

10.
int intA[0:5] = {1,2,3,4,5,6};
intA[2] = 3

  1. Homework
    how to insert an element at specific location
    how to delete an element at specific location
    how to reverse all the elements of the array
    what if we want to copy last 5 elements to another DA
    currently we can only copy the initial elements of the array.

SES#5

  1. associative array
    o hash, look up table
  2. Index values need not be continuous and need not start from 0.

int intA[9:0];
o what are indexes for above array? 0 to 9
o continous
int intA[100000];
o 0 to 99999
o this is the issue with fixed size arrays and dynamic arrays

  1. why we need associative array?
    o to verify very large memory(100000 locations), we don’t write to all the locations of the memory and read all the locations
    o randomly select 10 locations, write those locations, read back same locations
    o we will not allocate 100000 locations in TB memory TB refence model:
    reg [31:0] intAA[int];
    intAA[15] = data;
    intAA[39] = data;
    intAA[514] = data;
    so on allocate memory for 10 locations only.
    o we don’t need allocate 100000 locations, we can only allocate 10 locations
  1. Whenever design has a big memory, we want to model that behavior in TB
    o use associative array.
  2. data_type array_name[index_type];
  3. how index can be string?
    int intAA[string];
    intAA[“write”] = 32’h100; //”write” can be converted to equivalant ASCI value.
    intAA[“read”] = 32’h200;
    intAA[“erase”] = 32’h300;
    • what is associative array?
    • when to use associative array?
    • how to declare an associative array?
    • different methods?
  4. Queue
  5. homework
    Declare dynamic array of integers of size 10, Queue of integers of size 10, copy dynamic array elements to queue. Do reverse copy also.
    Write a logic to reverse the contents of dynamic array.
    Write a logic to add ‘1’ to all the elements of dynamic array.
    Write a logic to add ‘1’ to all the elements of the Queue.
    Declare 2 Queues of int, randomly populate with same number of elements with some fixed range values, compare both the Queues.
    Declare a DA of int and SA of int, randomly populate with same number of elements with some fixed range values, compare both the arrays.

10.
Declare a byte addressed memory of 64 locations
reg [7:0] mem[63:0];

Declare a word addressed memory of 128 locations

Declare a USB packet which has 128 nibbles(4 bits)
reg [127:0][3:0] packet;

SES#6

  1. OOP
  1. APB transaction class
    o APB
  2. Verilog
    o memory.v
    o tb_memory.v to verify the memory DUT
    o clock, rst declaration, generation
    o DUT instination
    o Generation of write/read transactions
    o Those txs driven on memory ports
    o displaying the values
    o report testcase pass/fail status
  3. Verilog based TB
    o everythin is done in single module
    o task, functions used
  4. SV based TB
    o divide everything in to sub blocks based on what they are supposed to do.
    o what all things we do as part of TB?
    o clock generation => Top module
    o reset generation => Top module
    o DUT instantiation => Top module
    o scenario generation => Generator
    o drive the scenario to the DUT => Driver(~BFM)
    o monitor the DUT input and output => monitor
    o give the monitored txs to the coverage and reference model
    o do the scenarion coverage => coverage
    o generate expected output => reference model
    o compare the actual output with the expected output => checker
    o keep track of overall status, report the status => scoreboard
    o protocol level checks => assertions analogy:
    – house
    – Very big room(~module), everything in that room ===> Verilog style
    – Very big room(~module), divide in to smaller rooms(~class objects), use those rooms(~class) for specific purpose => SV style
  5. connecitons
    module to module connecitons => ports
    module to class connecitons => interface (SV concept)
    class to class connecitons => mailbox (similar to FIFO)
  6. Simplest design with only one interface
    o memory
    o APB interface
  7. how does the APB tx look like
  8. nibble : 4
    byte : 8
    half word: 16
    word : 32
    DW : 64

10.
bit = 2 state variable (0, 1)
logic = 4 state variable (0, 1, x and z)

SES#7

revision:

  1. APB tx
    o properties
    o addr, data, wr_rd, sel
    o methods
    o print, copy, compare
    o constraints
    o addr, sel constraints
  2. apb_tx tx1, tx2;
    tx1 = tx2; //what is problem with this?
    both will point to same memory after that copy => they still continue to be depdent on each otehr.

Notes:

  1. Different types of copying
    • copy by handle tx1 = tx2; //copying the handle of tx2 to tx1
      • tx1 memory gets removed
        tx1.addr = 100; => tx2.addr also becomes 100
  2. int a, b;
    a = b;
    a = 30;
    does b get updated? No
    o hence we don’t to fix anything here.
  3. To solve this probelm, we use ‘shallow copy’
    • shallow copy is making sure that both objects are independet.
      o tx1. updates won’t tx2 fields, viceversa
  4. Even shallow copy has one problem.
    o if there is a object field inside the class, then shallow copy doesn’t work properly for those object fields.
    o for non-object fields it works
  5. ** Fatal: (SIGSEGV) Bad handle or reference.
    we are using an object, without memory allocation
  6. During shallow copy, object field handle gets copied to other object field handle.
    o hence they still tend to be depdennt(only for object fields)
    o for non-object fields, the value is getting copied.
  7. To solve the issue with shallow copy
    o deep copy
  8. How many types of copies
    o copy by handle
    o shallow copy
    o deep copy
  9. If a class doesn’t have any object fields, then there is no difference between shallow copy and deep copy.
  10. Deep copy = multiple levels of shallow copy
  11. class methods can be 2 types
    • language provided methods (LPM)
    • user implemented methods (UIM)
  12. copy => UIM
    compare => UIM
    print => UIM what are the LPM?
    o 4 methods
    o new => used for memory allocation to the object
    o pre_randomize => things we want to do(changes, fine tuning) before randomize is called
    o randomize => randomizing the class rand properties
    o post_randomize => things to do once randomize has happened
    o we can change the functionality of: new, pre_randomize and post_randomize
    o we can’t recode(change) the randomize method.
  13. “default values”

14.
So ‘this’ keyword refers to a built-in handle for a class?
yes.

15.
randomize comes with 2 callback methods: pre_randomize, post_randomize
o any time randomize is called, automatically pre_randomize and post_randomize also gets called.

pkt.randomize();

effect:
pkt.pre_randomize(); //fine tuning: some updates before randomization
pkt.randomize();
pkt.post_randomize(); //something after randomize is done
  1. callback methods
    drive_tx has two callback methods (pre_drive, post_drive) drive_tx(); effect:
    pre_drive(); //do the updates in this
    drive_tx();
    post_drive(); //do the updates in this using concept of callbacks, without changing the original function code, we can change the functionality.
  2. mailbox
    try_put => function
    try_get => function put, get => task mbox.get(tx); //if mailbox doesn’t have element to return, this method will block the execution
    mbox.try_get(tx); //if mailbox doesn’t have element to return, this method will not block the execution. It will continue to the next step.

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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