course overview:

  1. SV training
    3 aspects
    o SV language training
    o 7-8 weeks => expert with SV language
    o strong foundation with SV language constructs
    o AXI protocol and VIP development
    o 2-3 weeks
    o give exposure to coding and TB component development
    o Industry standard project
    o 5 weeks
    o give exposure to entire verification flow.
    o overall duration: 14 to 16 weeks
  2. Most of requirements
  3. schedule is similar to the one we had for Verilog


  1. why we need SV?
    o Verilog has few constructs(ex: for, always, etc), SV has lot of constructs
    o lot of constructs => more options in developing TB components => Hence SV makes TB development easier
  2. WHy we are moving SV?
  3. how to run with Questasim
    vlog top.sv
    add wave *
    run -all
  4. SV language concepts
  5. SV language basic constructs
  6. static and dynamic data types
    any memory allocation that happens at compile time(vlog top.sv) itself, it is called as ‘static’
    any memory allocation that happens at run time(run -all), it is called as ‘dynamic’
  7. Anytime we work with dyanmic data types, always use ‘new’ to create the memory
  8. SV = static data types + dynamic data types
    Verilog = static data types (no dynamic)
  9. Different phases of data type usage
    • Language provided
    • User defined data types
      Creation //for static datatype, Creation is not required(new)
      Process of allocating memory to the data variable
      ex: pkt=new();
  10. integer a; //static or dynamic?
  11. Constructs and Pre-implemented methods
    FIFO in Verilog
    user defined module?
    did we get FIFO defintiion from Verilog alngauge?
    everything in Verilog is User defined.
  12. in SV, language itself implements lot of things for us.
    FIFO(Verilog) => mailbox(SV)
    what operations we can do with FIFO?
    – read
    – write
    – reset
    – get the size of FIFO
    SV impelemtns above functions by default, user don’t need to implement these methods.
    – user just needs to understand, how to use these methods.
  13. Verilog, how much time taken to develop to FIFO?
    o 2-3 hours
    o in SV, we don’t need 2-3 hourse, since language itself provided the mailbox(~FIFO)
    – 2 minutes to acehive same

mbox = new(20); we can put maximum of 20 elements in to the mailbox
mbox = new(); we can put any number of elements in to the mailbox

  1. SV : common shared memory concept
  2. How Task, functions make Verilog code resuable and readable?
    o Mmeory TB => write_mem, read_mem
    o Same concept applies in SV also.
    o as much as possible, use task and functions while developing the code.
  3. mailbox
    new, put, get, try_put, try_get, peek, num
  4. Queue
    push_back, push_front, pop_back, pop_front, shuffle, insert, reverse, size
    • we don’t need to learn, how to implement above methods.
    • we only need to know, how to use these methods
  5. write a function, two input integer arguments(a,b), add numbers(a, b), return as function return value
    name of function : sum

function integer add(input integer a, input integer b);
add = a + b; //Verilog
return a + b; //SV

integer p, q, r;
use above function to add p, q and assign to r
r = add(p, q);

function void add(input integer a, input integer b, outout integer c);
c = a + b; //SV

integer p, q, r;
use above function to add p, q and assign to r

  1. homework
    Declare an array of word(reg [15:0]) data type, array size of 10. Fill it with random number between 20 to 30
    Declare another array of word data type, array size of 10. Fill it with random number between 20 to 30
    Write a logic to Compare elements of both the arrays.
    Declare an array of string data type, array size of 10. Assign elements with names from str1 to str10
    Declare another array of string data type, array size of 10. Assign elements with names from str1 to str10
    Write a logic to Compare elements of both arrays.

Dynamic Arrays
Size is allocated at the run time. Size can be changed during the run time.
integer intDA[ ]; //Dynamic array
integer intAA[*]; //Associative array
integer intAA[string]; //Associative array
integer intQ[$]; //Queue
Declare a dynamic array of word data type, allocate size of 10. Fill it with random number between 20 to 30
Declare a fixed size array of word data type, array size of 10. Fill it with random number between 20 to 30
Write a logic to compare elements of both arrays.




module sample1;
module sample2;
function sum(sample1 s1, sample2 s2); //Not possible

class sample1;
class sample2;
function sum(sample1 s1, sample2 s2); //possible: objects/class can be task/function argeumtns

SV : Hardware Description & Verification Language (HDVL)
o can be used for verification purpose also
Verilog: HDL

  1. Vera is HVL developed by Synopsys.
    o 2000 – 2005 time frame
    o Companies prefer using Vera(OOP language), compared to Verilog for TB development
    o when they use Vera, they have to use VCS tool(only that tool support)
  2. homework
    • example to show difference between bit and logic
  3. range of int
    int a;
    int is 32 bit signed variable.
    -231 to 231-1

n bit signed variable: -2n-1 to (2n-1) – 1

shortint: 16 bit
– decimal format : -32768 to 32767

function void print(); //this function does not return any value. Use void
//not retutrning anything

  1. string str;
    str = “verilog”; //7 bytes
    str = “system verilog”; //14 bytes
    str = “”; //0 bytes
  2. String comparison
    comp_f = 0 => compare has matched
  3. how to reverse a string. => homework
    for, putc => Hint


  1. string data type
    o sting methods
  2. string reversal


  1. Operators
    • Verilog operators
    • SV added operators
  2. streaming Operators
    o ethernet frame : preamble(56), SOF(8), DA(48), SA(48), LEN(16), PAYLOAD(46-1500 bytes), CRC(32)
    o data transfer between laptops will happen through Ethernet frames. 1st clock cycle
    preamble[55:48] data will go
    2nd clock cycle
    preamble[47:40] data will go
    3rd clock cycle
    preamble[39:32] data will go
    so on sof will be sent
    DA will be sent
    so on
  3. convert ethernet frame fields in to Queue of bytes.
    o take one byte from queue every clock cycle and drive it to the interface.
    o when we drive all the bytes, whole packet would be transmitted. byte byteQ[$];
    so on
    • issue: this will become very long.
      streaming operators:
      byteQ = {<>byte{preamble, sof, da, sa, len, payload, crc}};
      back of QUeue? crc[7:0]
      front of QUeue? preamble[55:48]
      o cricket match streaming

byte byteQ[$];
so on

  1. multiply with 16
    what shift and how many? LS, 4
  2. multiply with 128
    what shift and how many? LS, 7
  3. divide with 64
    what shift and how many? RS, 6
  4. multiply with 65 (64 + 1)
    a << 6 a << 0 sum of above 2
  5. multiply a with 37 (convert 37 to addition 2** numebr)
    a << 5 (32)
    a << 2 (4)
    a << 0 (1)
    add 37

i++ => post inrmente operator




  1. string data type
  2. Book shelf
    12 books
    14 pages
    10 lines
    9 Englishwords
  3. totally how many words in book shelf = 121410*9
  4. if we give unique address to each book, how to declare the book shelf

word [13:0][9:0][8:0] book_shelf [11:0]; //if we give unique address to each book

  1. if we give unique address to each page, how to declare the book shelf
    o how many addresses are required in total = 12*14
    word [9:0][8:0] book_shelf [11:0][13:0]; //if we give unique address to each page
  2. if we give unique address to each word, how to declare the book shelf
    o how many addresses are required in total = 121410*9
    word book_shelf [11:0][13:0][9:0][8:0] ; //if we give unique address to each word
  3. if we give one address to whole book shelf, how to declare the book shelf
    o how many addresses are required in total = 1
    word [11:0][13:0][9:0][8:0] book_shelf;
  4. I want to refer to 7th book, 8th page, 6th line
    how many words does it represent? 9 words
  5. I want to refer to 5th book, 4th page, 9th line, 7th word
    book_shelf[5][4][9][7] => how many words? 1 word
  6. book_shelf[5] => how many words? 14109

multi_arr='{‘{‘{10, 9, 8, 7}, ‘{9, 8, 7, 6}, ‘{8, 7, 6, 5}}, ‘{‘{9, 8, 7, 6}, ‘{8, 7, 6, 5}, ‘{7, 6, 5, 4}}, ‘{‘{8, 7, 6, 5}, ‘{7, 6, 5, 4}, ‘{6, 5, 4, 3}}, ‘{‘{7, 6, 5, 4}, ‘{6, 5, 4, 3}, ‘{5, 4, 3, 2}}, ‘{‘{6, 5, 4, 3}, ‘{5, 4, 3, 2}, ‘{4, 3, 2, 1}}, ‘{‘{5, 4, 3, 2}, ‘{4, 3, 2, 1}, ‘{3, 2, 1, 0}}}

multi_arr[4][2][1]? 7
multi_arr[0][1][3]? 4
multi_arr[0][0][0]? 0

int intA[0:5] = {1,2,3,4,5,6};
intA[2] = 3

  1. Homework
    how to insert an element at specific location
    how to delete an element at specific location
    how to reverse all the elements of the array
    what if we want to copy last 5 elements to another DA
    currently we can only copy the initial elements of the array.


  1. associative array
    o hash, look up table
  2. Index values need not be continuous and need not start from 0.

int intA[9:0];
o what are indexes for above array? 0 to 9
o continous
int intA[100000];
o 0 to 99999
o this is the issue with fixed size arrays and dynamic arrays

  1. why we need associative array?
    o to verify very large memory(100000 locations), we don’t write to all the locations of the memory and read all the locations
    o randomly select 10 locations, write those locations, read back same locations
    o we will not allocate 100000 locations in TB memory TB refence model:
    reg [31:0] intAA[int];
    intAA[15] = data;
    intAA[39] = data;
    intAA[514] = data;
    so on allocate memory for 10 locations only.
    o we don’t need allocate 100000 locations, we can only allocate 10 locations
  1. Whenever design has a big memory, we want to model that behavior in TB
    o use associative array.
  2. data_type array_name[index_type];
  3. how index can be string?
    int intAA[string];
    intAA[“write”] = 32’h100; //”write” can be converted to equivalant ASCI value.
    intAA[“read”] = 32’h200;
    intAA[“erase”] = 32’h300;
    • what is associative array?
    • when to use associative array?
    • how to declare an associative array?
    • different methods?
  4. Queue
  5. homework
    Declare dynamic array of integers of size 10, Queue of integers of size 10, copy dynamic array elements to queue. Do reverse copy also.
    Write a logic to reverse the contents of dynamic array.
    Write a logic to add ‘1’ to all the elements of dynamic array.
    Write a logic to add ‘1’ to all the elements of the Queue.
    Declare 2 Queues of int, randomly populate with same number of elements with some fixed range values, compare both the Queues.
    Declare a DA of int and SA of int, randomly populate with same number of elements with some fixed range values, compare both the arrays.

Declare a byte addressed memory of 64 locations
reg [7:0] mem[63:0];

Declare a word addressed memory of 128 locations

Declare a USB packet which has 128 nibbles(4 bits)
reg [127:0][3:0] packet;



  1. OOP
  1. APB transaction class
    o APB
  2. Verilog
    o memory.v
    o tb_memory.v to verify the memory DUT
    o clock, rst declaration, generation
    o DUT instination
    o Generation of write/read transactions
    o Those txs driven on memory ports
    o displaying the values
    o report testcase pass/fail status
  3. Verilog based TB
    o everythin is done in single module
    o task, functions used
  4. SV based TB
    o divide everything in to sub blocks based on what they are supposed to do.
    o what all things we do as part of TB?
    o clock generation => Top module
    o reset generation => Top module
    o DUT instantiation => Top module
    o scenario generation => Generator
    o drive the scenario to the DUT => Driver(~BFM)
    o monitor the DUT input and output => monitor
    o give the monitored txs to the coverage and reference model
    o do the scenarion coverage => coverage
    o generate expected output => reference model
    o compare the actual output with the expected output => checker
    o keep track of overall status, report the status => scoreboard
    o protocol level checks => assertions analogy:
    – house
    – Very big room(~module), everything in that room ===> Verilog style
    – Very big room(~module), divide in to smaller rooms(~class objects), use those rooms(~class) for specific purpose => SV style
  5. connecitons
    module to module connecitons => ports
    module to class connecitons => interface (SV concept)
    class to class connecitons => mailbox (similar to FIFO)
  6. Simplest design with only one interface
    o memory
    o APB interface
  7. how does the APB tx look like
  8. nibble : 4
    byte : 8
    half word: 16
    word : 32
    DW : 64

bit = 2 state variable (0, 1)
logic = 4 state variable (0, 1, x and z)





  1. APB tx
    o properties
    o addr, data, wr_rd, sel
    o methods
    o print, copy, compare
    o constraints
    o addr, sel constraints
  2. apb_tx tx1, tx2;
    tx1 = tx2; //what is problem with this?
    both will point to same memory after that copy => they still continue to be depdent on each otehr.


  1. Different types of copying
    • copy by handle tx1 = tx2; //copying the handle of tx2 to tx1
      • tx1 memory gets removed
        tx1.addr = 100; => tx2.addr also becomes 100
  2. int a, b;
    a = b;
    a = 30;
    does b get updated? No
    o hence we don’t to fix anything here.
  3. To solve this probelm, we use ‘shallow copy’
    • shallow copy is making sure that both objects are independet.
      o tx1. updates won’t tx2 fields, viceversa
  4. Even shallow copy has one problem.
    o if there is a object field inside the class, then shallow copy doesn’t work properly for those object fields.
    o for non-object fields it works
  5. ** Fatal: (SIGSEGV) Bad handle or reference.
    we are using an object, without memory allocation
  6. During shallow copy, object field handle gets copied to other object field handle.
    o hence they still tend to be depdennt(only for object fields)
    o for non-object fields, the value is getting copied.
  7. To solve the issue with shallow copy
    o deep copy
  8. How many types of copies
    o copy by handle
    o shallow copy
    o deep copy
  9. If a class doesn’t have any object fields, then there is no difference between shallow copy and deep copy.
  10. Deep copy = multiple levels of shallow copy
  11. class methods can be 2 types
    • language provided methods (LPM)
    • user implemented methods (UIM)
  12. copy => UIM
    compare => UIM
    print => UIM what are the LPM?
    o 4 methods
    o new => used for memory allocation to the object
    o pre_randomize => things we want to do(changes, fine tuning) before randomize is called
    o randomize => randomizing the class rand properties
    o post_randomize => things to do once randomize has happened
    o we can change the functionality of: new, pre_randomize and post_randomize
    o we can’t recode(change) the randomize method.
  13. “default values”

So ‘this’ keyword refers to a built-in handle for a class?

randomize comes with 2 callback methods: pre_randomize, post_randomize
o any time randomize is called, automatically pre_randomize and post_randomize also gets called.


pkt.pre_randomize(); //fine tuning: some updates before randomization
pkt.post_randomize(); //something after randomize is done
  1. callback methods
    drive_tx has two callback methods (pre_drive, post_drive) drive_tx(); effect:
    pre_drive(); //do the updates in this
    post_drive(); //do the updates in this using concept of callbacks, without changing the original function code, we can change the functionality.
  2. mailbox
    try_put => function
    try_get => function put, get => task mbox.get(tx); //if mailbox doesn’t have element to return, this method will block the execution
    mbox.try_get(tx); //if mailbox doesn’t have element to return, this method will not block the execution. It will continue to the next step.


  1. declare two arrays of apb_tx
    • size of the array : 5
      txarr1, txarr2
    • randomize both the elements
      compare both the array elements =< they won’t match, display message
    • copy one array to anotehr
      compare both the array elements =< they match, display message
  2. Elements in TB can be divided in to 2 categories
    o TB components => class
    o BFM, Generator, Monitor, coverage, reference model, checker
    o these compoennts gets created at sim time=0, exist till the end of the simulation($finish).
    o TB Transaction classes => class
    o Packet, apb-tx, axi_tx, eth_frame
    o these elmenets gets created during the simulation, they get used, and then gets deleted.
  3. TB transaction classes: 2 types
    o frame or packet (for any peripheral bus protocol)
    o eth_frame, usb_frame, pcie_packet
    o print, copy, compare, pack, unpack
    o transactions (for any on chip protocol)
    o axi_tx, apb_tx, ahb_tx, ocp_tx
    o print, copy, compare
    o pack, unpack : are not required.
  4. can we print a BFM? No, hence print is not required
    is there anything like packing BFM? No
  5. OOP
    o encapsulation
    o concept of grouping properties+methods+constraints into single element
    o concept of data hiding
    o flexibility of user to decide what level of protection to give for each element.
    o inheritance
    o polymorphsim
  6. analogy
    o old building form their parents => construct new building => changing the property definition
  7. XMR: any thing can be changed in module hierarchy
  8. car
    class swift extends car;

class creta extends car;

10 swift cars
5 creta cars


  1. total 4 testcases
    • mix of all pkts
    • only good pkts
    • only bad pkts
    • only ill pkts
  2. testcases are impelemnted in eth_gen.sv
    o inside task run
    o case statement
    o testcases are impelemnted as case branches.
  3. Next improvement
    • we are keeping variables in global scope. Instead keep in a class scope and use everywhere.
  4. Next improvement
    • mbox not a static variable
    • create mbox in eth_env
      o pass mbox handle to gen and bfm as function new argument
      o assign it to local mbox handle
  5. During inheritance, function and task prototypes must be same(no change at all)
  6. casting
    metal items => melt => idols ==> Metal Casting

virtual class uvm_monitor;
uvm_monitor mon;
mon = new(); //not possible

can you kindly share the lab and theory schedule?
Mon-Sat : 1:30PM to 6:00PM
1:30PM to 3:30PM : Theory
4Pm to 6PM : Labs


  1. eth_common
    o this is the class or file, where we keep the things that are shared(accessed) by different TB components.
    o ex:
    – Generator requires testname(to read testname) and top module requires testname(update)
  2. WHy do we get FATAL error: Bad handle or reference
    o use an object handle, which is not yet allocated(create)
  3. Why top should be module,it should be class possible
    o module can be elaborated
    vsim work.
    element must be a module only
  4. near “=”: syntax error, unexpected ‘=’, expecting function or task or “SystemVerilog keyword ‘pure'”.
    I found no syntaxes error here, yet it gave this error..
  5. can v put all the classes in the same sv file? sir.


  1. real use cases of Polymorphsim
    o Polymorphsim is useful wherever we have one generator generating ‘different types of packets’, all being put in to the same mailbox. BFM needs to figure out what packet is coming out of mailbox.
    o Here we use concept of Polymorphsim
    o get all the packets in to base_class handle, call all the task and functions on base_class handle only.
    o if task/function is defined as virtual, concept of polymorphism automatically works.
    pkt.print(); //if print is virtual, pkt will be understood good/bad/illegal automatically.

2Q. packet can get by order in bfm without polymorphism

  1. multi level inheritance
  2. FIFO and LIFO
  1. what is the benefit of parameterized class?
    o we can use the same class for different requirements, without developing a new file.
    o we can also use for different FIFO depth.
  2. Furhter updates
    o we can use the same class to behave like LIFO or FIFO
    o we don’t have to develop lot of files or lot of classes => most imp benefit.
  3. how to implement inheritance in parameterized classes.




  1. Parameterized class
    o for all practical purpose, what has been done so far, is sufficeint.
  2. Analogy: specialization
    MBBS -> MD (with different specialization)
    o cardiologist
    o neurologist

o give lot of emphasisi on learning basic of parameterized classes.
o even if you have to skip specialization and inheritance in parameterized classes.

  1. Parameterized classes with inheritance
  2. static properties and mehtods
    o is a way of creating a commonly shared database, which can be accessed anywhere in the testbnech.
  3. SV already provides concept of parameter and macro, hence we don’t need constant concept.




  1. parameterized class
  2. parameterized classes with inheritance
  3. static properties and static methods
  4. interface class
  5. constant (const)
    o global constant
    o instance constant


  1. scope resolution operator
  2. Nested class
  3. $cast
    o dynamic casting
    o static casting
  4. Data types
  5. revision


  1. SV language basics
  2. Arrays
    o static and dynamic arrays
    o associative arrays
    o Queue
  3. basic data types
  4. Operators
  5. OOP
  6. scopre resolution operator
    • one data type defined inside anotehr data type, to separate them, we use :: operator
  7. Nested classes
    o A class defined inside anotehr class => Nested class
    o why do we want to define a class inside anotehr class?
    o this concept is useful if we want to create a databases, that need to be accessed by complete testbench.
  8. We will not be using Nested class in SV course
    • it is a widely used concept in UVM
  9. $unit:: ==> use :: for $unit global scope
    $root.top. => use . for $root
  10. object copying
    4 types of copying
    – copy by handle
    – shallow copy
    – deep copy
    – $cast
  11. $cast is similar to copy by handle with a very impornta difference.
    class eth_pkt

eth_pkt pkt;
eth_good_pkt g_pkt;
eth_bad_pkt b_pkt;

mbox.get(pkt); //pkt is actually one of g_pkt/b_pkt/i_pkt
g_pkt = pkt; //is not allowed => SV language won’t allow
//SV language doesn’t allow assigning a base handle to dereived class handle.

  1. There are cases where ‘copy by handle’ doesn’t work, in all those cases $cast might be a solution.
    o except for this $cast and copy by handle are both doing same work.
    o we are not creating any new memory for destination object.
    o $cast is a improved version of ‘copy by handle’
  2. OOP
    • OOP is a very important concept => Whole SV TB development is about OOP concepts only.
    • OOP
      o encapsulation
      o concept of grouping the properties+methods+constraints in to same unit
      o concept of data protection/hiding by using local/protected
      o inheritance
      o concept of inheriting all the properties, methods and constraints in to the derived class.
      o inheritance : major advantage, it reduces the overall coding effort.
      o this, super.
      o super makes sure that, we are able to reuse the base class method in the derived class.
      o what is meant by property overriding?
      o what is meant by method overriding?
      o what is meant by constraint overriding?
      o polymorphsim
      o when one generator is generating multipel types of packets.


  1. casting
    o two types
    o static casting
    o int -> byte
    o string -> integer
    o dynamic casting
    o object -> object
  2. $cast (base_class_object, derived_class_object); => general usage
  3. if we are getting on object from mailbox as base_class_object(actually it is derived_class_object)
    $cast(derived_class_object, base_class_object_one_we_got_from_mailbox);
    derived_class_object = base_class_object_one_we_got_from_mailbox; //not possible directly like this

data types:

  1. c-handle (chandle)
  2. event
  3. user defined data types


  1. c-handle (chandle)
    o handle coming from C language
    o handle called in C language? pointer
    o when we need to get a pointer from C program in to SV code, it is done using chandle.
  2. why do we need to get pointer from C program -> SV code?
    o DPI : Direct programming interface
    o improved version of PLI or VPI
  3. DPI?
    o Involves SV program calling the functions defined in C program. => Importing of functions
    o Involves C program calling the task/functions defined in SV program. => Exporting of task/functions
    o while calling these task/functions, we can pass some data variables as arguemtns.
    o ex: int, both C, SV support int => hence there is no issue.
  4. 99.99% you will never use chandle.
  5. DPI
    o reference model is implemented in C programming(or C++)
    o rest of TB is using SV and UVM
    o there we use concept of DPI to connect both these programs.
  6. user defined data types
    o we have discussed the data types provided by the language.
    o int, integer, byte, string, bit, etc
    o SV langauge gives a provision for user to defined their own data types.

I need a data type which represents 8 bit signed variable => byte
I need a data type which represents 16 bit signed variable => shortint
I need a data type which represents 64 bit signed variable => longint
what if I need to represent 4 bit signed variable data type?
o No
o User can define their own data type.

bit signed [3:0] nibble; => nibble is a data variable
this can be changed to data type(User defined datatype)

typedef bit signed [3:0] nibble_t; => nibble_t represents a datatype.
nibble_t a, b, c; //a represents a signed 4 bit variable.

  1. int intA[3:0];
    I want to intA as a data type
    typedef int intA_t[3:0]; //intA_t is a datatype(not data vairbale), it rpresents int array of 4 size
    intA_t intA1, intA2; //intA1 : data type or variable? variable(array of 4 integers)
  2. typedef string strA[1:0]; //strA is a data type

typedef class sample; //no need of typedef, it is by default understood.

  1. Array of Queue of apb_tx’s (array size of 10)

11Q. can we use multidimensional queue here
since we know 7 queue are only thre
o we prefer using Array of queues.

  1. typedef
    o we can use typedef to create a complex multi dimensional data structures.

Declare array of array of integer, top level: 3 size, lower array: 5 size
Declare array of queue of bytes
Array size of 5
Use nested for loops.
As much as possible use foreach for interaction.

In this example, can we use struct data type?
what all things to keep struct data type?
o name of country
o gold
o silver
o bronze

think of doing same problem using Verilog?
o half a day
o SV we cna do in 15 mins

87, 56, 78, 45 => sort(ascending order) => 45, 56, 78, 87
87, 56, 78, 45 => rsort(descending order) => 87, 78, 56, 45

  1. project
    o Tokyo olympics




  1. Declare a queue of arrays
    o queue size is 3
    o array size is 5
    o fill this multi dimensional array with unique number between 20 to 40


  1. union
  2. enum
  3. Labeling
  4. process
  5. IPS constructs


  1. union
    o not an important data type
  2. APB architecture with 4 slaves
    o there I can use enum

enum {
SLAVE_0 = 4’b0001,
SLAVE_1 = 4’b0010,
SLAVE_2 = 4’b0100,
SLAVE_3 = 4’b1000
} slave_target_t;
sel = 4’b1000;
sel = SLAVE_3; //better

  1. resp_t resp_1, resp_2;
  2. mbox.try_get(a);
    if mbox is empty, try_get will not wait, it proceeds to the next line without waiting for data.




  1. CHandle
  2. Struct
  3. Enum
  4. Union


  1. IPS constructs


  1. What is IPS?
    o various processes happening in different components
    o acheiving synchronization between these components => IPS
  2. mailbox
    o when one component is generating the data
    o when other component is consuming the data
    o to synchornize this data flow => mailbox
  3. mailbox
    2 types
    – parameterized
    – non-parameterized
  4. mailbox #(integer) mbox;
    mbox.put(“sv”); //it won’t allow
    mbox.put(10); //possible
  5. mailbox provides blocking nature
    o put and gets are the tasks.
  6. Queue has only functions
    o push_back and pop_front are the functions
  7. Can we use Queue to connect generator to BFM?
    o it is possible
  8. event
    o Verilog: non-persistant triggered nature
    o only allows one process to wait
    o in a given time step, wait should be happening first -> after that only trigger should happen => Then only event will be caught.
    o timescale 10ns/10ps o if event is triggered at 13ns o wait at 17ns => event will not be caught. o Verilog style: @(e); => non-persistant triggered nature o SV: persistant triggered nature o multiple processes can wait for the same event o in a given time step, whatever order trigger happens and wait happens => event will still be caught otimescale 10ns/10ps
    o if event is triggered at 13ns
    o wait at 17ns => event will be caught.
    o SV style: wait(e.triggered()); => persistant triggered nature
  9. to indicate the event is not triggered
    e = null(); //event is not triggered
  10. semaphore
    o it is used in requirement, where we can’t fullfill that suing mailbox or event.
  11. I have a TB where this kind of scenario is tehre, where same resource being accessed by multiple compoents(processor)
    o TB update to fix this problem will be for 2 minutes work smp = new(1); //1 : number of keys smp.get(1); //added line
    smp.put(1); //added line smp.get(1); //added line
    smp.put(1); //added line o P1 and P2 can’t happen at same time, eitehr of them can only happen




  1. memory
  2. TB for memory
    o stage#1 : BFM, generator
    o see txs happening at the interface
    o write and read data matching.
    o stage#2 : multiple set of BFM, generator
    o stage#3 : monitor and coverage
    o stage#4 : reference model


  1. any testbench has 2 types of elements
    o module
    o class(objects)
  2. various connections in testbench
    o module to module connection
    o ports
    o ex: hierarchical modeling(mem_ctrl)
    o class to class connection
    o mailbox
    o module to class connection
    o can we use ports? No => class doesn’t have ports.
    o can we use mailbox? yes => we don’t use, since mailbox is non-synthesizable.
    o solution?
    o interface
  3. stage#1 : basic template is setup => no functionality impelmetned
    stage#2 : impelment the functionality of all the components




  1. stage#2 : multiple set of BFM, generator


  1. is it issue with BFM memory allocation?

task run();
axi_tx tx;
forever begin
mbox.get(tx); //lets say mbox has 10 txs
join_none //don’t wait for any process to complete, jsut move on to next execution

task drive_tx_to_intf(axi_tx tx); //task => blocking => unless this gets over, next line won’t start

  1. fork join => running TB components concurrently
    fork join_none => implementing overlapping transactions
    fork join_any => implementing handshaking checks or scenario where we only want one process to complete(others should be killed)
  2. 5 writes and 5 reads
    3 agents
    total txs(both wr and rd) = 30 waveform: 10 handshakings => 10 txs
    o instead of 30 txs, why only 10 txs are happening?



o stage#3 : monitor and coverage
o stage#4 : reference model


  1. monitor
    o monitor interface signals, collect the transactions, give those txs to other components(coverage, ref model)
  2. except for generator, all other compoennts in TB are forever running compoentns

3.analogy: 1 to 100, divide in 10 ranges =>
1-10 : 5 times
11-20 : 2 times
21-30 : 0 times
31-40 : 0 times
41-50 : 2 times
51-60 : 2 times
61-70 : 1 times
71-80 : 1 times
81-90 : 2 times
91-100 : 0 times
how many bins?
we ran the simulation. 70%, miss=30%
what should I do now?
o run simulation to make sure, we cover missing 30% also

  1. configurable TB
    o we are able to change the TB structure as per our requirements.
  2. why semaphore can’t be declared inside mem_bfm?
    //semaphore smp = new(); => why semaphore can’t be declared here?
    o when we create the TB, multiple instiances of BFM will get created
    o it will result in multiple semaphore created
    o synchronizaiton can’t be acehvied
    o hence we create one common semaphore in mem_common and refer to that everywhere
  3. Memory TB is a very important project
    o If you can do all by yourself without refering to video or code => then you will gain expertise with SV.
  4. updates done to fix the monitor issue
    o introduced a concept of clocking block and modport
    o what is clocking block?
    o design inputs => When the BFM should drive design inputs, what is the right time, so that DUT can capture those values properly.
    o design output => When the BFM should sample design output, what is the right time, so that BFM gets proper values.




  1. Interface
    o can be used for many things.
    primary uses: => just by using clocking block => everything else is not importnat
    – bundling of the signals in to one single entity
    – proper sampling of design outputs ==> clocking block
    – proper driving of design inputs secondary uses: - we can write assertions inside interface => this can be done in other components of TB also. - we can implement tasks(for driving txs) inside interface - we can also implement coverage inside interface
  2. clocking block
    o tells to the BFM,
    o when to drive design inputs, so that design will capture those inputs properly
    o when to sample design outputs, so that BFM will get proper values of design output.
  3. many times, in actual projects, we face issue related to signal driving and sampling.
    o due to values are not captured properly(either by BFM or DUT), hence testcase fails.
    o Looking at waveform, everything looks fine, why signal is not captured properly?
    o answer: use clocking block.
  4. clocking block
    o input skew
    o BFM: how much time ‘before the +edge’ of the clock, design output(~BFM input) should be sampled
    o output skew
    o BFM: how much time after the +edge of the clock, design input(~BFM output) should be driven
  5. output skew
    • setup time
      o Minimum time before the +edge of clock, for which duration DFF input value must be stable.
    • what is best time to give input to the design?
      o drive the input ‘just after’ the +edge of the clock, so that it will be captured at next edge of the clock.
      o just after ==> output skew

192933892893 x 783278238 = => every 10 minutes I give a question
o 1 minute : do you have answer => wrong answer
o 5 minute : do you have answer => wrong answer
o 9 minute : do you have answer => wrong answer
o 10th minute : do you have answer => wrong answer ==> since I am giving 10 minutes, this is best chance of getting right answer.
147834 x 7847843 = => every 10 minutes I give a question
o 10th minute: next question =>

  1. just before: ‘input skew’
  2. SV language doesn’t tell, what is right value of input and output skew
    o it is decided based on current requirements.
    o look at the waveform =>
    o take a set of input and output skew values => run a simulation -> check if design and TB behavior is proper => then it is the proper skew value.
    o if it didn’t work => what went wrong => change the skew => run again => till we reach a point where design and TB behavior is proper.
  3. memory : monitor is not working properly
    o if we do 10 writes, it is capturing only 9
    o if we do 2 writes, it is capturing only 1
    o it is missing 1st tx or last tx? => 1st tx
  4. monitor is having a sampling issue =>
    o solution: use clocking block
  5. concept of different outputs using different skews, is only for learning purpose.
    • in practice, we don’t need to use different skew values.
    • mostly importnat is default skew.

12Q. How do we know that descrepency in op is because of the skew only and not other factors ? How do we conclude or cancel out other possibilities ?
o descrepency started wtih monitor collecting same txs two times
o why monitor is collecting two times?
o go to the waveform

Interview questions?
How clocking block helps avoid race conditions?
What is input skew and output skew?
Why <= is used for driving interface signals? How do we decide skew values? what is default skew? Why modport is required? o redundant o it is used to define the port directions => since it is anyway done in clocking block, it becomes redundant.
o modport: module port directions
@(intf.bfm_cb) what does this mean?
Can we see where the sampling is happening in the waveform?
What is physical interface and virtual interface?

  1. modport is meant to be used in design RTL coding.
    o interface, we want to use it in design code, by default there are no directions.
    o how to define directions? modport
    o use this modport in the design.
  2. interface
    o how to define inputs, signals
    o clocking block => TB purpose
    o modport => Design purpose
  3. module => physical interface
    class => virtual interface
  4. 20 hours
    o interfave: 19.5 hours
    o scheudling scemants: .5 hours
  5. Verilog
    o timestep : 4 regions
    o active, inactive, NBA, monitored SV:
    o timestep : 13 regions
    o why more regions?
    o because SV has more constructs(ex: mailbox, intf, semphaore)
  6. clear distinction between design related region and TB related region in the timestep => make sure that there is no metastiablity conditions in design and TB execution.
  7. program
    o redundant, companies now don’t use it.
    o Mentor graphics clearly tells not to use it. o what is program block? why is it redundant?
    o adding an additional layer between top module and TB compoennts
    o we don’t want to call env.run in the top module, we want to call it in program initial
    o why do we want to do that? o earlier : env.run() => module initial block
    o env.run() => TB related actiivty(event), by calling it in module initial, it is getting called in active region, which falls under Design specific part of the timestep. That specific call we want to do in TB related regiion.
    o we intrudce program block, there you call env.run() => reactive region
    o this helps avoid the possible race conditions at time=0, when we just call env.run()
    o actully at time=0, things are just starting, there is no question of race condition b/w DUT and TB. Hence no need of program block.
    o program : en.run() => program initial block
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