Schedule: Every Monday, 2PM to 5:30PM

1. Email Etiquette

2. English Grammar rules

3. Conference etiquette

4. Office etiquette

5. Creating resume

6. Working in team

7. Facing interviews

8. Group discussions

Softskill training:

1. Email Etiquette
   1. Avoiding multiple mail exchanges, keeping it precise
      1. Whom to include in the email
   1. How to write a mail
      1. Subject line:
   1. How to address recipients
   1. How to put the content
   1. Whom to include in the mail
2. English Grammar rules
   1. pronunciation

3. Meeting & Conference etiquette

4. Office etiquette

5. Creating resume

          –

– 2 pages maximum

          – more complex project first in the list

          –

6. Working in team

• Understanding responsibilities
• Working as per timelines
• How to give time estimate to manager

7. Facing interviews

• Tell about self
• Summarizing overall technical expertise
• Talking confidently

8. Group discussions

• Understanding the given topic
• Listing down all relevant points
• Should be able to talk for 15 minutes

https://grammar.yourdictionary.com/grammar-rules-and-tips/basic-english-grammar-rules.html

https://www.townandcountrymag.com/society/a10276858/office-etiquette/

Growth in career in directly related to both technical expertise and soft skills.

Simple essay writing

– tell about yourself? in 100 words

I am Sreenivas. I was born and brought up in Anantapur. I am a post graduate with specialisation in VLSI Design. I have been working since last 14 years. My last job was with UST Global. My hobbies are reading books. On professional side, I like to pursue my career in VLSI design and verification.

Tell about your technical expertise?

What projects you have worked on?

• Projects, skillset, languages

Freshers in verification domain:

• What is the other person wants to listen? What is he interested in?
• I have completed 6 months training in Functional verification. During this period, I have been trained on Verilog, SV, and UVM. I also have expertise on/in standard protocols based on AMBA, Ethernet, Memory based protocols. I have worked on projects based on these protocols, which includes VIP Development, complete functional verification for Memory controller. I also have expertise on Questasim tool. I am also good with Linux OS and PERL scripting.

Physical Design:

• I have done a 6 months training in Physical Design. During this period, I have been trained on complete PnR flow, which includes Synthesis to Physical verification. I have worked on multiple projects at 28nm using Synopsys flow. One of the projects is multi voltage domain project, and another is a chip level implementation project. Project flow was implemented using Design compiler, ICC2, PT, StarRC and IC validator. During this, I have gained exposure to input files, import design, floorplan, power planning, placement, SDF generation, ECO closure and Physical verification. I am also good with TCL based flow implementation.

Things to focus:

• Content, how we build the content
• Grammar
• Confidence in presenting the things

DFT, Layout

Grammatical mistakes:

i am sreenivas i was born and brought up in Anantapur, Andhra Pradesh. I am a post graduate with specialisation in VLSI Design. I has been working for last 14 years at Bangalore. My last job was with UST Global. My hobbies are reading books. On professional side, I like to pursue my career in VLSI design and verification.

————-

English Grammar Rules:

– Noun, verb, adverb, pronoun, adjective, preposition

– where to use full stop, comma, semicolon, apostraphe

– where to use new line and where to use line continuation

– where to is, was, had, have, am, will, etc

– where to use capital

    o Name, Noun, new sentence, new paragraph

– where to write new paragraph

Context:

I am working on a project. some debug support I need. I need to send mail to design engineer for the support.

How to start the mail

2 possibilities:

• He knows you
  • No need to introduce
• He doesn’t know you
  • Give a brief introduction.

 2 possibilities:

• He knows that you are working on the project
• He does not know

Hi Ramesh,

Subject line: Debug support with processor subsystem testcases

Introduction:

————–

I am Sreenivas, working on Snapdragon M885 SOC verification, based out of Bangalore. I work on processor sub system top level verification.

Content of the mail

During last regression, some of the processor subsystem testcases have failed. I have debugged the failing tests, I see a possible issue with prefetch block. Below is the debug analysis.

• RTL Tag name:
• Transaction is not coming at proper address on Processor subsystem at master interface.
• Traced this transaction to decode block, figured that issue is with transaction coming from prefetch block to decode block. At this interface, address is corrupted.
• Debugged further in to prefetch block, see a possible issue with the way instruction is fetched.
• This behaviour is violating design specification.
• Below is the waveform with issue highlighted.
  • Paste the waveform image here
  • Paste the RTL code snipping here(where the logic is wrong)
• How to view the waveform:
  • Waveform path
  • DO file path

How to conclude the mail

Can you please confirm if above is a known issue? Please let me know required updates to fix this issue.

Regards,

Sreenivas

Leave application:

Context: Dhashara, 1 week leave

Subject: one week leave from 15 to 22/Oct

How to start

Content (To whom we are writing mail)

How to conclude

MAIL TO MANAGER:

Hi Ramesh,

NO NEED TO TELL ABOUT YOUSELF

How to start:

I would like to take one week leave from 15/Oct to 22/Oct during Dhasara festival.

Content(if you are project/block which is critical)

I am working on Processor subsystem verification. I have completed 80% of testcases. All of them except 2 tests are passing. I will try to close these tests before I go on vacation. I will be creating a document with quick notes on my testcases, so that other team members can support in my absence.

How to conclude:

Request you to grant the leave.

Regards,

Sreenivas

——

4. Office etiquette

• Being in office during working hours(when most of the other team members are available)
• Not to talk loudly over phone
• Dress code
• Be available at the cubicle for more time
• Not to go out office for long time(more than 30 minutes) without informing manager or lead
• Be polite with other people
• When you meet new people, how to introduce yourself, shake hands

5. Creating resume

• One page or maximum 2 pages.
• Keep important projects(one which you are confident) in the beginning
• Mention what employer might be interested in
  • HDL
  • HVL
  • Protocol
  • Tools
  • Scripting
  • Architecture expertise
  • Any certifications
• Creating resume:
  • Name | Email | Phone | Location
  • Profile Summary:
    • A graduate with 6 months training in Functional verification. using Verilog, SV, and UVM with expertize on VIP Development, complete functional verification using constraint random verification and coverage driven verification.
  • Experience/academic
    • ME/MTech, Specialization, YOP, College_name, %
    • BE/BTech, Specialization, YOP, College_name, %
    • 12^th/Diploma
  • Skill Set
    • HDL
    • HVL
    • Scripting
    • EDA Tools
    • OS
  • Projects: (You SHOULD BE ABLE TO TALK ABOUT THESE PROJECTS FOR ATLEAST 10 MINUTES)
    • Complex project first
    • Put all the relevant projects
• Resume1.pdf
• R101.pdf
• Resume naming:
  • Name_Highest_Degree_YOP_Experitize.pdf
  •