1. explain the project
2. Responsibilities
3. explain TB architecture
4. what all features are there in your block
5. how test cases were developed, does it use C?
6. How C & SV interaction(handshake) happens?
7. Explain testplan?
8. explain design architecture
9. explain design subcomponents?
10. develop testcase
11. what is GPIO
o non maskable interrupt
12. how to debug testcase
13. what is tarmac log
14. what is the processor in the soc
15. what is the frequency
16. did you find any bugs(issues in the rtl)
17. what kind of testcases did you develop
18. explain one testcase flow in detail
19. what is list file, MPF file, scatter file
20. how many memories were there in SOC
21. how memory preloading works
22. what is boot sequence? what happens during boot?
23. what is the reset sequence?
24. what are the usecases for the SDIO(design you worked on)?
25. How SDIO VIP is integrated in to SOC testbench
26. what is MMU(memory management unit)
26. did you develop a test with multiple processor involved?
27. did you work on performance testcases, what is performance tst
28. did you work on low power(power aware) testcases, what is low power tst
29. how did you verify registers in the design, did you register layer from UVM
30. what is interrupt service routine? explain how interrupt from SDIO is handled by the processor?
31. explain various types of interrupts generated by SDIO
32. explain the SDIO(block in resume) architecture, what all ports it has, how it connects to VIP
33. what is pad muxing?
34. how did you diagnose a bug, how it was validated
35. Develop testbench components?
36. explain how scoreboarding is done?
37. what is cache? what is cache coherency?
38. how is cache coherency implemented?
39. what is virtual address? physical address in SOC?
40. how messaging happens in C testcases
SV : $display
but printf can’t be used on SOC, SOC TB will use a separate mechanism for printing messages
41. What is the clock frequency supported by your block?
42. what is performance requirements? how did you check that?
43. what is veloce platform?
44. Block specific questions
45. develop a piece of C testcase, SV testcases
46. develop a ARM instruction
for loop implement using ARM instruction
47. how testbench flow works?
Does C code start first?
Does SV code start first?
48. How C code convert to image?
what is ARM Compiler (armcc)
what is ARM linker (armcc)
what is the image, how it is loaded to memory?
how processor boots from this image?
49. how does synchronisation happen between processors?
semaphore
50. debug tools used
Verdi
FSDB
51. what is derivative project?
52. what revision management was used?
53. did you use any verification management system?
54. how to you close verification? regression, 100% toggle coverage
55. Difference between Cortex M, A, R series
56. clock generation, was it internally generated or externally generated
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