1. RTL Design
    o RTL Implementation for a given design
    Combinational logic
    truth table to arrive at the required logic
    karnuagh maps
    Sequential logic
    FSM implementation
    Synchronizer implementation
    CDC : Clock domain crossing : Signal moves from one clock domain to another clock domain
    o CDC always results in metastability, to avoid metastability, we add 2-stage or 3-stage synchronizers in between these clock domains
    Register logic
    Connecting multiple blocks to each other : logic implementation at those boundaries
    o RTL Integration
    Connecting multiple blocks to each other : logic implementation at those boundaries
  2. PISO, SIPO using FIFO
  3. Synchronizer (3 stage)

signal moving from clk1 to clk2

module 3stage_sync(d, q3);
always @(posedge clk2) begin
q1 <= d;
q2 <= q1;
q3 <= q2;
end
endmodule

q3 : 3 stage synchronized signal WRT clk2 domain

  1. During RTL design & integration
  2. setup time, hold time, clock frequency
    setup time: minimum amount of time for which D input must be stable before +edge of clock, so that output takes the value of D input
    hold time: minimum amount of time for which D input must be stable after +edge of clock, so that output takes the value of D input
    how clock frequency is related to setup time:

STA:

If a design has 100 FF’s, there will be alteast 99 ‘2-ff’ combinations
SDF : Standard Delay Format

always @(posedge clk) begin
q <= d;
end

SDF annotation:

STA analysis is done using Primetime tool.
PVT(Process voltage temparate) variation results in different delay values for same logic
o one corner gives best case timing
o anoterh corner gives worst case timing

Setup violation:
o D input at capture flop is reaching late and violating the setup time of capture flop
How to fix Setup violatin:
o

Setup time equation:
LFF_CLK_TO_Q + COMB_DLEAY + SETUP_TIME <= CLOCK_TP + CLOKC_PATH_DELAY_BW_LAUNCH_AND_CAPTURE_FLOP

HVT and LVT cells to change gate specific delay values

Hold time equation:
COMB_DLEAY >= Hold time
it has no relation to clock frequency

Hold time violation fixing:
Increase the COMB_DLEAY

  1. writing standalone testbenches
    power down controller
    input ports, output ports
  2. mealy, moore

5 states:

Gray code counter : how gray code counter avoids meta stability or glitches at design boundaries

  1. design constraints
  2. DFF, TFF
  3. what kind of issues can be there in a design code
  1. block statements and non-blocking statements
    non-blocking statements: kind of statements, whose RHS value gets captured and assignment to LHS is scheduled for end of timestep
    blocking statements: kind of statements, whose RHS value gets captured and assignment to LHS happens immeditely
  2. always use non-blocking statements when implemneting sequential logic
  3. always use blocking statements when implemneting combinational logic
  4. Hierarchical modeling
  5. RTL CDC checks
    The CDC flow is a verification tool flow which reads the RTL source files, checks for missing or inadequate synchronization logic and reports them back to the engineer.
  6. Lint checks
    Lint, on the other hand, is a verification tool flow which checks the RTL source code for inconsistent coding style that would potentially lead to Synthesis vs Simulation mismatches.
  7. how a code infers a latch, what do we do avoid latches
    i. if case is tehre, always use ‘default’
    ii. if statement: always write else
    iii. if or case, always initialize the value before case/if

BELOW CODE INFERS LATCH:
always@(*)
if (something)
nothing = 0;
else if (something_else)
nothing = 1;

BELOW CODE INFERS COMBINATIONAL LOGC:
always@(*)
nothing = 0;
if (something)
nothing = 0;
else if (something_else)
nothing = 1;

  1. Metastability
  1. Difference between race condition and metastability

swapping of 2 numbers using blocking assignments : Race condition
setup or hold violation of DFF will result in metastability
glitch : Asynchous FIFO results in glitches -> which can further result in metastability

  1. Async FIFO
    always @(posedge rd_clk) begin
    //wr_ptr_rd_clk <= wr_ptr;
    wr_ptr_gray_rd_clk <= wr_ptr_gray;
    end

wr_ptr : 4’b0111
when we do a write, wr_ptr will be = 4’b1000

0111 -> 0101 -> 0100 -> 0000 -> 1000
if above 3 intermediate states, matches with rd_ptr value, it will results in empty glitch

Solution:

21.
reg [3:0] d;
always @(posege clk) begin
q1 = d;
q2 = q1;
q3 = q2;
end
above code synthesizes to 4 FF (1 state having 4 FF, all 4 FF are parallel)

22.
reg [3:0] d;
always @(posege clk) begin
q1 <= d;
q2 = q1;
q3 <= q2;
end
above code synthesizes to 8 FF (4 FF per stage)

  1. Write a funciton to covert binary to gray code
  2. Design implementaiton questions
    up-counter implementaiton using only Gates:

always @(posedge clk) begin
if (rst) count <= 0;
else count <= count + 1;
end

up-counter can also be impelmented using gates only:
C2C1C0 N2N1N0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Karnaugh map:
N2 = c2bc1c0 + c2c1b + c2c0b
N1 = c1^c0
N0 = ~c0;

Does it require any sequential elements or is it purely combinational?
o if the output is dependent on current state and inputs, then it is sequential
o if the output is only dependent on inputs, with no dependence on curerny output or current state, then it is combinational

module up_counter();

and g1(n1, cb[2], c[1], c[0]);
and g2(n2, c[2], cb[1]);
and g3(n3, c[2], cb[0]);
xor g4(n4, c[1], c[0]);
or g5(n5, n1, n2, n3);
dff g6(c[2], n5, clk, rst);
dff g7(c[1], n4, clk, rst);
dff g8(c[0], cb[0], clk, rst);
endmodule

module dff();
endmodule

  1. Implement 3 bit FA using gates only
  2. Synthesizable code

################################################################

SESSION-2

  1. STA
    2 FF’s
    launch flop
    cpature flop
  1. CDC
    o CDC metastability
    o by addiing 2 or 3 stage synchronizer on the destnation clock domain
  2. Glitches comes since we enter in to unwanted state for short duration of
    time
    o avoid those state transitions
  3. non synthesizable codes
    wait();
    repeat(2) @(posdge clk);
    @(posedge clk);

5;

  1. RTL engineer
    State machines
  2. where do we need state macines?
    Interrupt controller?
    list down the states of a design?
    S_NO_ACTIVE_INTR
    S_INTR_GIVEN_TO_PROC
    S_INTR_SERVICED_BY_PROC

always @(posdge clk) begin
case (state)
“S_NO_ACTIVE_INTR” : begin
if (intr_in != 0) begin
next_state = S_INTR_GIVEN_TO_PROC;
end
end
“S_INTR_GIVEN_TO_PROC” : begin
if (intr_servd == 1) begin
next_state = S_INTR_SERVICED_BY_PROC;
end
end
“S_INTR_SERVICED_BY_PROC” : begin
end
endcase
end

always @(next_state) begin
state = next_state;
end

  1. SPI Controller

always @(posedge sclk) begin
case (spi_data_state)
“S_NO_DATA” : begin
end
“S_TX_DATA” begin
data_o = data[count];
count = count +1;
if (count == 8) begin
tx_done = 1;
next_spi_data_state = S_NO_DATA;
end
end
“S_RX_DATA” begin
end
endcase
end

always @(posdge clk) begin
case (state)
“S_IDLE” : begin
if (tfr_req == 1) begin
next_state = S_ADDR;
end
end
“S_ADDR” : begin
/*
for(i=0; i < 8; i=i+1) begin
@(posedge sclk);
mosi = addr[i];
end
*/
spi_data_state = S_TX_DATA;
if (tx_done == 1) next_state = S_IDLE_BW_ADDR_DATA;
end
“S_IDLE_BW_ADDR_DATA” : begin
next_state = S_DATA:
end
“S_DATA” : begin
for(i=0; i < 8; i=i+1) begin
@(posedge sclk);
mosi = data[i];
end
next_state = S_IDLE;
end
endcase
end

always @(next_state) begin
state = next_state;
end

  1. RTL integration
  2. PISO using FIFO

module piso(clk, rst, data_i, valid_i, ready_o, data_o, valid_o, ready_i)
//assign wr_en = valid_i;
//assign ready_o = full;

//to generate wr_en to FIFO, following conditions should meet
//1. valid_i = 1
//2. full = 0
always @(posedge wr_clk) begin
wr_en = 0;
if (valid_i & ~full) begin
wr_en = 1;
wdata = data_i;
end
end
async_fifo fifo_i(wr_clk, rd_clk, rst, wdata, wr_en, rdata, rd_en);

always @(posedge rd_clk) begin
case (tx_state)
“S_NO_TRANSMIT” : begin
//transmit_in_progress_f = 0;
if (~transmit_in_progress_f && ~empty) begin
rd_en = 1;
next_tx_state = S_READ_FROM_FIFO;
end
end
“S_READ_FROM_FIFO” : begin
rd_en = 0;
transmit_in_progress_f = 1;
transmit_data_on_serial(rdata);
transmit_in_progress_f = 0;
end
//”S_TRANSMIT_IN_PROGRESS” : begin
//end
endcase
end

task transmit_data_on_serial(input reg [7:0] data);
begin
for (int i = 0; i < 8; i=i+1) begin
@(posedge clk_out);
data_o = data[i];
end
end
endtask

/*
always @(posedge rd_clk) begin
rd_en = 0;
if (~transmit_in_progress_f && ~empty) begin
rd_en = 1;
@(posedge rd_clk);
//tx_data = rdata;
transmit_data_on_serial(rdata);
end
end
*/
endmodule

31 Q: Digital design complete
it creates a pattern:
011 -> 100 -> 010 -> 101

32 Q:
a = x~z + ~yz
f = (x~z + ~yz)~y + xy = x~y~z + ~yz + xy = x + ~yz

33.
1010
1’s compl: 0101
2’s compl: 1010 + 1 = 1011

1st stge : 1011
2nd stage: 0100 -> 1011 + 1 = 1100
3rd stage: 0011 -> 1100 + 1 = 1101

34.
Puzzle (number max, min):
3 cascaded :
1 2 3 4 => 2 1 4 3 => 2 4 1 3 => 4 2 3 1 => 4 3 2 1 => 4 3 2 1
4 3 2 1 => 4 3 2 1 => 4 2 3 1 => 4 2 3 1 => 4 3 2 1 => 4 3 2 1
4 1 2 3 => 4 1 3 2 => 4 3 1 2 => 4 3 2 1 => 4 2 3 1 => 4 2 3 1

Next solution:
1 2 3 4 => 2 1 4 3 => 2 4 1 3 => 4 2 3 1 => 4 2 3 1 => 4 3 2 1
4 3 2 1 => 4 3 2 1 => 4 3 2 1 => 4 3 2 1 => 4 3 2 1 => 4 3 2 1
4 1 2 3 => 4 1 3 2 => 4 3 1 2 => 4 3 1 2 => 4 3 2 1 => 4 3 2 1
3 1 4 2 => 3 1 4 2 => 3 4 1 2 => 3 4 1 2 => 4 3 2 1 => 4 3 2 1

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